Synchronous Serial Port LH79524/LH79525 User’s Guide14-2 Version 1.0Table 14-1 describes these modes.For all three formats, the serial clock (SSPCLK) is held inactive while the SSP is idle andtransitions at the programmed frequency only during active transmission of data. TheSSPCLK pin can be HIGH during idle in SPI Mode if the SPO bit in the Control Register is set.For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame(SSPFRM) pin is active LOW and asserted (pulled down) during the entire frame transmis-sion. Both formats output data on the falling edge of the clock and latch input data on therising edge of the clock.Table 14-1. Feature ComparisonMODE DESCRIPTION DATA TRANSFERS COMMENTSPILets the SSP communicatewith Motorola SPI-compatibledevices.Full-duplex, 4-wiresynchronousClock polarity and phaseare programmable.SSILets the SSP communicatewith Texas Instruments DSP-compatible Serial SynchronousInterface devices.Full-duplex, 4-wiresynchronousMicrowireLets the SSP communicatewith National SemiconductorMicrowire-compatible devices.Half-duplex synchronous,using 8-bit controlmessages
