Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 21 page image

7 Series DSP48E1 User Guide www.xilinx.com 21UG479 (v1.10) March 27, 2018DSP48E1 Slice PrimitiveDSP48E1 Slice PrimitiveFigure 2-4 shows the DSP48E1 primitive. It also shows the input and output ports of theDSP48E1 slice along with the bit width of each port. The port definitions are in Table 2-2.X-Ref Target - Figure 2-4Figure 2-4: DSP48E1 Slice PrimitiveA[29:0]B[17:0]C[47:0]OPMODE[6:0]ALUMODE[3:0]CARRYINCARRYINSEL[2:0]CEA 1CEA 2CEB 1CEB 2CECCEDCEMCEPCEADRSTARSTBACOUT[29:0]BCOUT[17:0]PCOUT[47:0]P[47:0]CARRYOUT[3:0]CARRYCASCOUTMULTSIGNOUTPATTERNDETECTPATTERNBDETECTOVERFLOWUNDERFLOWRSTCRSTDRSTMRSTPRSTCTRLRSTALLCARRYINCLKRSTALUMODERSTINMODEACIN[29:0]BCIN[17:0]PCIN[47:0]CARRYCASCINMULTSIGNINCEALUMODECECTRLCECARRYINCEINMODE301848D[24:0]2530184848743INMODE[4:0]54301848UG369_c1_04_051209Send Feedback