Xilinx 7 Series User Manual

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7 Series DSP48E1 User Guide www.xilinx.com 47UG479 (v1.10) March 27, 2018Chapter 3DSP48E1 Design ConsiderationsThis chapter describes some design features and techniques to use to achieve higherperformance, lower power, and lower resources in a particular design.This chapter contains the following sections:• Designing for Performance• Designing for Power• Adder Tree Versus Adder Cascade• Connecting DSP48E1 Slices across Columns• Time Multiplexing the DSP48E1 Slice• Miscellaneous Notes and Suggestions• Pre-Adder Block ApplicationsDesigning for PerformanceTo achieve maximum performance when using the DSP48E1 slice, the design needs to befully pipelined. For multiplier-based designs, the DSP48E1 slice requires a three-stagepipeline. For non-multiplier-based designs, a two-stage pipeline should be used. Also seethe 7 series FPGA data sheets [Ref 6]. If latency is important in the design and only one ortwo registers can be used within the DSP48E1 slice, always use the M register.Designing for PowerThe USE_MULT attribute selects usage of the multiplier. This attribute should be set toNONE to save power when using only the Adder/Logic Unit. Functions implemented inthe DSP48E1 slice use less power than those implemented in fabric. Using the cascadepaths within the DSP48E1 slice instead of fabric routing is another way to reduce power. Amultiplier with the M register turned on uses less power than one where the M register isnot used. For operands less than 25 x 18, fabric power can be reduced by placing operandsinto the MSBs and zero padding unused LSBs.Send Feedback