Xilinx 7 Series User Manual

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40 www.xilinx.com 7 Series DSP48E1 User GuideUG479 (v1.10) March 27, 2018Chapter 2: DSP48E1 Description and SpecificsEmbedded FunctionsThe embedded functions in 7 series devices include a 25 x 18 multiplier,adder/subtracter/logic unit, and pattern detector logic (see Figure 2-14).Pre-adderThe 7 series FPGA DSP slice has a 25-bit pre-adder, which is inserted in the A register path(shown in Figure 2-14 with an expanded view in Figure 2-7, page 30). With the pre-adder,pre-additions or pre-subtractions are possible prior to feeding the multiplier. Since the pre-adder does not contain saturation logic, designers should limit input operands to 24-bittwo’s complement sign-extended data to avoid overflow or underflow during arithmeticoperations. Optionally, the pre-adder can be bypassed, making D the new input path to themultiplier. When the D path is not used, the output of the A pipeline can be negated priorto driving the multiplier. There are up to 10 operating modes, making this pre-adder blockvery flexible.In Equation 2-2, A and D are added initially through the pre-adder/subtracter. The resultof the pre-adder is then multiplied against B, with the result of the multiplication beingadded to the C input. This equation facilitates efficient symmetric filters.Equation 2-2X-Ref Target - Figure 2-14Figure 2-14: Embedded Functions in a DSP48E1 SliceX17-Bit Shift17-Bit Shift0YZ100484818434830BCIN* ACIN*OPMODEPCIN*MULTSIGNIN*PCOUT*CARRYCASCOUT*MULTSIGNOUT*CREG/C Bypass/MaskCARRYCASCIN*CARRYINCARRYINSELA:BALUMODEBACMPP PCMULT25 X 18PATTERNDETECTPATTERNBDETECTCARRYOUTUG369_c1_14_0521094748483018PP*These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.5D 2525INMODEACOUT*183043018Dual B RegisterDual A, D,and Pre-adder1Adder/Subtracter Output C B D A±( )× C IN+( )±=Send Feedback