Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 76 page image

76 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 3: Transmitter5. TX Pattern Generator, page 1036. TX Pattern Generator, page 1037. TX Polarity Control, page 1068. TX Fabric Clock Output Control, page 1079. TX Configurable Driver, page 11410. TX Receiver Detect Support for PCI Express Designs, page 12111. TX Out-of-Band Signaling, page 123FPGA TX InterfaceFunctional DescriptionThe FPGA TX interface is the FPGA’s gateway to the TX datapath of the GTP transceiver.Applications transmit data through the GTP transceiver by writing data to the TXDATA port on thepositive edge of TXUSRCLK2. The width of the port can be configured to be two or four byteswide. The actual width of the port depends on the TX_DATA_WIDTH attribute and TX8B10BENport setting. Port widths can be 16, 20, 32, and 40 bits. The rate of the parallel clock (TXUSRCLK2)at the interface is determined by the TX line rate, the width of the TXDATA port, and whether or not8B/10B encoding is enabled. A second parallel clock (TXUSRCLK) must be provided for theinternal PCS logic in the transmitter. This section shows how to drive the parallel clocks andexplains the constraints on those clocks for correct operation.Interface Width ConfigurationThe 7 series FPGA GTP transceiver contains a 2-byte internal datapath. The FPGA interface widthis configurable by setting the TX_DATA_WIDTH attribute. When the 8B/10B encoder is enabled,the TX_DATA_WIDTH attribute must be configured to 20 bits or 40 bits, and in this case, the FPGATX interface only uses the TXDATA ports. For example, TXDATA[15:0] is used when the FPGAinterface width is 16. When the 8B/10B encoder is bypassed, the TX_DATA_WIDTH attribute canbe configured to any of the available widths: 16, 20, 32, or 40 bits.Table 3-1 shows how the interface width for the TX datapath is selected. 8B/10B encoding isdescribed in more detail in TX 8B/10B Encoder, page 83.When the 8B/10B encoder is bypassed and the TX_DATA_WIDTH is 20 or 40, theTXCHARDISPMODE and TXCHARDISPVAL ports are used to extend the TXDATA port from 16to 20 bits, or 32 to 40 bits. Table 3-2 shows the data transmitted when the 8B/10B encoder isdisabled. When the TX gearbox is used, refer to TX Gearbox, page 86 for data transmission order.Table 3-1: FPGA TX Interface Datapath ConfigurationTX8B10BEN TX_DATA_WIDTH FPGA InterfaceWidthInternal DataWidth1 20 16 2040 32 200 16 16 1620 20 2032 32 1640 40 20Send Feedback