Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 169 page image

7 Series FPGAs GTP Transceivers User Guide www.xilinx.com 169UG482 (v1.9) December 19, 2016RX 8B/10B DecoderRX 8B/10B DecoderFunctional DescriptionIf RX received data is 8B/10B encoded, it must be decoded. The GTP transceiver has a built-in8B/10B encoder in the GTP transceiver TX and an 8B/10B decoder in the GTP transceiver RX,which includes two one-byte 8B/10B decoder modules on the datapath to decode data withoutconsuming FPGA resources. The RX 8B/10B decoder has these features:1. Supports 2-byte and 4-byte datapath operation2. Provides daisy-chained hookup of running disparity for proper disparity3. Generates K characters and status outputs4. Can be bypassed if incoming data is not 8B/10B encoded5. Pipes out 10-bit literal encoded values when encountering a not-in-table error8B/10B Bit and Byte OrderingThe order of the bits into the 8B/10B decoder is the opposite of the order shown in Appendix C,8B/10B Valid Characters. 8B/10B decoding requires bit a0 to be received first, but the GTPRXSLIDE_MODE String Defines the RXSLIDE mode.OFF: Default setting. The RXSLIDE feature is not used.PCS: PCS is used to perform the bit-slipping function. RXSLIDE is drivenHigh for one RXUSRCLK2 cycle to shift the parallel data (RXDATA) to theleft by one bit within the comma alignment boundary determined by theALIGN_COMMA_WORD and RX_DATA_WIDTH settings. In this mode,even if RXOUTCLK is sourcing from the RX PMA, the clock phase remainsthe same. This option requires SHOW_REALIGN_COMMA to be FALSE.PMA: PMA is used to perform the bit-slipping function. RXSLIDE is drivenHigh for one RXUSRCLK2 cycle to shift the parallel data (RXDATA) to theright by one bit. If RXOUTCLK is sourcing from the RX PMA, its phasemight be changed. This mode provides minimum variation of latencycompared to PCS mode. This option requires SHOW_REALIGN_COMMAto be FALSE.AUTO: This is an automated PMA mode without using the FPGA logic tomonitor the RXDATA and issue RXSLIDE pulses. In this mode, RXSLIDEis ignored. In PCIe applications, this setting is used for FTS lane deskew.This option requires SHOW_ALIGN_COMMA to be FALSE.RXSLIDE_AUTO_WAIT Integer Defines how long the PCS (in terms of RXUSRCLK clock cycle) waits for thePMA to auto slide before checking the alignment again. Valid settings are from0 to 15. The default value is 7. The recommended value from the 7 SeriesFPGAs Transceivers Wizard should be used.RX_SIG_VALID_DLY Integer Reserved. The recommended value from the 7 Series FPGAs TransceiversWizard should be used.COMMA_ALIGN_LATENCY 6-bit Binary Current alignment used by the byte align block to align the incoming data basedon the comma location locked. This register is only accessible via the DRP:Bits[6:0] of DRP address 0x150Table 4-26: RX Byte and Word Alignment Attributes (Cont’d)Attribute Type DescriptionSend Feedback