Xilinx 7 Series User Manual

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Xilinx 7 Series User Manual Manual pdf 164 page image

164 www.xilinx.com 7 Series FPGAs GTP Transceivers User GuideUG482 (v1.9) December 19, 2016Chapter 4: ReceiverManual AlignmentRXSLIDE can be used to override the automatic comma alignment and to shift the parallel data.RXSLIDE is driven High for one RXUSRCLK2 cycle to shift the parallel data by one bit. RXSLIDEmust be Low for at least 32 RXUSRCLK2 cycles before it can be used again.Figure 4-31 shows the waveforms for manual alignment using RXSLIDE in RXSLIDE_MODE =PCS, before and after the data shift. When RXSLIDE_MODE = PCS is used, the number of bit shiftpositions when consecutive RXSLIDE pulses are issued is also determined by the comma alignmentboundary set by ALIGN_COMMA_WORD and RX_DATA_WIDTH. For example, if theRX_DATA_WIDTH is 20 bits and ALIGN_COMMA_WORD is 1, after the 9th slide operation, theslide position returns back to 0. For the same RX_DATA_WIDTH setting, for anALIGN_COMMA_WORD setting of 2, the slide position returns to 0 after the 19th slide operation.Note relevant to Figure 4-31:1. Latency between the slide and the slide result at RXDATA depends on the number of active RXPCS blocks in the datapath.X-Ref Target - Figure 4-31Figure 4-31: Manual Data Alignment Using RXSLIDE for RX_DATA_WIDTH = 20 Bits andRXSLIDE_MODE = PCSUG482_c4_20_111011RXUSRCLK2RXSLIDERXDATATXDATA 0000000000100111110000000000000010011111 0000000000100111110000000000000100111110Slide results on RXDATAafter several cycles of latencythrough the PCS pathA minimum of 32 RXUSRCLK2cycles are required between twoRXSLIDE pulsesSend Feedback