CHAPTER 3: INSTALLATION PILOT CHANNEL COMMUNICATIONSL30 LINE CURRENT DIFFERENTIAL SYSTEM – INSTRUCTION MANUAL 3-4133.4.4.3 Transmit timingThe RS422 interface accepts one clock input for transmit timing. It is important that the rising edge of the 64 kHz transmittiming clock of the multiplexer interface is sampling the data in the center of the transmit data window. Therefore, it isimportant to confirm clock and data transitions to ensure proper system operation. For example, the following figureshows the positive edge of the Tx clock in the center of the Tx data bit.Figure 3-43: Clock and data transitions3.4.4.4 Receive timingThe RS422 interface utilizes NRZI-MARK modulation code and therefore does not rely on an Rx clock to recapture data.NRZI-MARK is an edge-type, invertible, self-clocking code.To recover the Rx clock from the data-stream, an integrated digital phase lock loop (DPLL) circuit is utilized. The DPLL isdriven by an internal clock, which is 16-times over-sampled, and uses this clock along with the data-stream to generate adata clock that can be used as the serial communication controller (SCC) receive clock.3.4.5 Two-channel two-clock RS422 interfaceThe two-channel two-clock RS422 interface (module 7V) is for use with the synchrophasor feature. The figure shows themodule connections.
