GE L30 Instruction Manual

Also see for L30: Communications manual Communications guide Instruction manual Instruction manual Instruction manual

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GE L30 Instruction Manual Manual pdf 610 page image

10-12 L30 LINE CURRENT DIFFERENTIAL SYSTEM – INSTRUCTION MANUALOVERVIEW CHAPTER 10: THEORY OF OPERATION10Sequence numbers are also used to match messages for the protection computation. Whenever a complete set of currentmeasurements from all terminals with matching sequence numbers are available, the differential protection function iscomputed using that set of measurements.10.1.14 Start-upInitialization in our peer-to-peer architecture is done independently at each terminal. Relays can be turned on in any orderwith the power system either energized or de-energized. Synchronization and protection functions are accomplishedautomatically whenever enough information is available.After a relay completes other initialization tasks, such as resetting of buffer pointers and determining relay settings, initialvalues are computed for any state variables in the loop filters or the protection functions. The relay starts its clock at thenominal power-system frequency. Phaselet information is computed and transmitted.• Outgoing messages over a given channel are treated in the same way as during the channel recovery process. Thespecial start-up message is sent each time containing only a single time step value.• When incoming messages begin arriving over a channel, that channel is placed in service and the loop filters arestarted up for that channel.• Whenever the total clock uncertainty is less than a fixed threshold, the phase locking filter is declared locked anddifferential protection is enabled.10.1.15 Hardware and communication requirementsThe average total channel delay in each direction is not critical, provided that the total round trip delay is less than fourpower-system cycles. The jitter is important and needs to be less than ±130 μs in each direction. The effect of a differencein the average delay between one direction and the other depends on the number of terminals. In the case of a two orthree-terminal system, the difference is not critical, and can even vary with time. In the case of four or more terminals,variation in the difference limits the sensitivity of the system.• The allowable margin of 130 μs jitter includes jitter in servicing the interrupt generated by an incoming message. Forboth incoming and outgoing messages, the important parameter is the jitter between when the time stamp is readand when the message begins to go out or to come in.• The quality of the crystal driving the clock and software sampling is not critical, because of the compensationprovided by the phase and frequency tracking algorithm, unless it is desired to perform under or over frequencyprotection. From the point of view of current differential protection only, the important parameter is the rate of drift ofcrystal frequency, which needs to be less than 100 parts per million per minute.• A 6 MHz clock with a 16-bit hardware counter is adequate, provided that the method described in this document isused for achieving the 32-bit resolution• An eight-bit time stamp is adequate provided that time-stamp messages are exchanged once per cycle• A four-bit message sequence number is adequateDepending on the 87L settings, channel asymmetry (the difference in the transmitting and receiving paths channel delay)cannot be higher than 1 to 1.5 ms if channel asymmetry compensation is not used. However, if the relay detectsasymmetry higher than 1.5 ms, the 87L DIFF CH ASYM DET FlexLogic operand is set high and the event and target are raised(if they are enabled in the CURRENT DIFFERENTIAL menu) to provide an indication about potential danger.10.1.16 Online estimate of measurement errorsGE's adaptive elliptical restraint characteristic is a good approximation to the cumulative effects of various sources of errorin determining phasors. Sources of error include power system noise, transients, inaccuracy in line charging currentcomputation, current sensor gain, phase and saturation error, clock error, and asynchronous sampling. Errors that can becontrolled are driven to zero by the system. For errors that cannot be controlled, all relays compute and sum the error foreach source of error for each phase. The relay computes the error caused by power system noise, CT saturation,harmonics, and transients. These errors arise because power system currents are not always exactly sinusoidal. Theintensity of these errors varies with time, for example growing during fault conditions, switching operations, or loadvariations. The system treats these errors as a Gaussian distribution in the real and in the imaginary part of each phasor,