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ARM720T Core cpu
Epson ARM720T Core Cpu Manual
Epson ARM720T Core Cpu Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
About the ARM720T processor
Figure 1-1 720T Block diagram
Figure 1-2 ARM720T processor functional signals
Coprocessors
Table 1-1 Key to tables
Figure 1-3 ARM instruction set formats
Table 1-2 ARM instruction summary
Table 1-3 Addressing mode 2
Table 1-4 Addressing mode 2 (privileged)
Table 1-7 Addressing mode 4 (store)
Table 1-11 Condition fields
Figure 1-4 Thumb instruction set formats
Table 1-12 Thumb instruction summary
Silicon revisions
Processor operating states
Memory formats
Instruction length
Operating modes
Figure 2-3 Register organization in ARM state
Figure 2-4 Register organization in Thumb state
Figure 2-5 Mapping of Thumb state registers onto ARM state registers
Program status registers
Table 2-2 PSR mode bit values
Exceptions
Table 2-3 Exception entry and exit
Table 2-4 Exception vector addresses
Relocation of low virtual addresses by the FCSE PID
Reset
Implementation-defined behavior of instructions
About configuration
Internal coprocessor instructions
Registers
Figure 3-4 Control Register read format
Figure 3-6 Translation Table Base Register format
Figure 3-7 Domain Access Control Register format
Figure 3-9 Fault Address Register format
Figure 3-10 FCSCE PID Register format
About the instruction and data cache
IDC validity
About the write buffer
Write buffer operation
About the bus interface
Figure 6-1 Simple AHB transfer
Bus interface signals
Figure 6-2 AHB bus master interface
Transfer types
Figure 6-4 Transfer type examples
Address and control signals
Table 6-3 Burst type encodings
Slave transfer response signals
Data buses
Table 6-6 Active byte lanes for a 32-bit little-endian data bus
Arbitration
Bus clocking
About the MMU
access permissions and domains
MMU program-accessible registers
Address translation
Figure 7-2 Translating page tables
Figure 7-3 Accessing translation table level one descriptors
Table 7-2 Level one descriptor bits
Figure 7-5 Section descriptor
Figure 7-7 Fine page table descriptor
Figure 7-8 Section translation
Table 7-7 Level two descriptor bits
Figure 7-10 Large page translation from a coarse page table
Figure 7-11 Small page translation from a coarse page table
Figure 7-12 Tiny page translation from a fine page table
MMU faults and CPU aborts
Fault address and fault status registers
Domain access control
Table 7-11 Interpreting access permission (AP) bits
Fault checking sequence
External aborts
About coprocessors
Table 8-1 Coprocessor availability
Coprocessor interface signals
Pipeline-following signals
Coprocessor interface handshaking
Figure 8-1 Coprocessor busy-wait sequence
Figure 8-2 Coprocessor register transfer sequence
Figure 8-4 Coprocessor load sequence
Connecting coprocessors
Not using an external coprocessor
About debugging your system
Controlling debugging
debug modes
Entry into debug state
Figure 9-4 Clock synchronization
Debug interface
The EmbeddedICE-RT macrocell
Disabling EmbeddedICE-RT
EmbeddedICE-RT register map
The debug communications channel
Table 9-2 Domain Access Control Register bit assignments
Scan chains and the JTAG interface
Table 9-3 Instruction encodings for scan chain 15
The TAP controller
Public JTAG instructions
Test data registers
Table 9-5 Scan chain number allocation
Scan timing
Examining the core and the system in debug state
Exit from debug state
The program counter during debug
Priorities and exceptions
Watchpoint unit registers
Figure 9-12 EmbeddedICE-RT block diagram
Figure 9-13 Watchpoint control value, and mask format
Programming breakpoints
Programming watchpoints
Debug control register
Table 9-10 Interrupt signal control
Debug status register
Figure 9-17 Debug control and status register structure
Coupling breakpoints and watchpoints
EmbeddedICE-RT timing
About the ETM interface
Connections between the ETM7 macrocell and the ARM720T processor
Clocks and resets
About the ARM720T test registers
Automatic Test Pattern Generation (ATPG)
Test State Register
Figure 11-2 Rd format, CAM read
Figure 11-4 Rd format, RAM read
Figure 11-9 Data format, CAM match RAM read
MMU test registers and operations
Table 11-5 CAM, RAM1, and RAM2 register c15 operations
Figure 11-12 Rd format, CAM write and data format, CAM read
Figure 11-14 Data format, RAM1 read
Figure 11-16 Rd format, write TLB lockdown
Table A-1 AMBA interface signals
A.2 Coprocessor interface signals
A.3 JTAG and test signals
A.4 Debugger signals
A.5 Embedded trace macrocell interface signals
A.6 ATPG test signals
CORE CPU MANUAL
ARM720T Revision 4
(AMBA AHB Bus Interface Version)
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ARM720T Core cpu
