4: Instruction and Data CacheARM720T CORE CPU MANUAL EPSON 4-14 Instruction and Data CacheThis chapter describes the instruction and data cache. It contains the following sections:4.1 About the instruction and data cache ....................................................... 4-14.2 IDC validity ................................................................................................ 4-24.3 IDC enable, disable, and reset................................................................... 4-24.1 About the instruction and data cacheThe cache only operates on a write-through basis with a read-miss allocation policy and arandom replacement algorithm.4.1.1 IDC operationThe ARM720T contains an 8KB mixedInstruction and Data Cache (IDC).The cache comprises four segments of 64 lines each, each line containing eight words. The IDCis always reloaded a line at a time. The IDC is enabled or disabled using the ARM720T ControlRegister and is disabled on HRESETn.Note: The MMU must never be disabled when the cache is on. However, you can enablethe two devices simultaneously with a single write to the Control Register (seeControl Register on page 3-4).4.1.2 Cachable bitThe C bit determines if data being read can be placed in the IDC and used for subsequent readoperations. Typically, main memory is marked as cachable to improve system performance,and I/O space is marked as noncachable to stop the data being stored in the ARM720T cache.For example, if the processor is polling a hardware flag in I/O space, it is important that theprocessor is forced to read data from the external peripheral, and not a copy of the initial dataheld in the cache. The cachable bit can be configured for both pages and sections.Cachable reads (C=1)A line fetch of eight words is performed when a cache miss occurs in a cachable area of memory,and it is randomly placed in a cache bank.Note: Memory aborts are not supported on cache line fetches and are ignored.Uncachable reads (C=0)An external memory access is performed and the cache is not written.
