3: Configuration3-6 EPSON ARM720T CORE CPU MANUAL3.3.4 Domain Access Control RegisterReading from CP15 Register 3 returns the value of the Domain Access Control Register.Writing to CP15 Register 3 writes the value of the Domain Access Control Register.The Domain Access Control Register consists of 16 2-bit fields, each of which defines the accesspermissions for one of the 16 domains (D15-D0).The CRm and opcode_2 fields Should Be Zero when reading or writing to CP15 Register 3.Domain Access Control Register format is shown in Figure 3-7.Figure 3-7 Domain Access Control Register format3.3.5 Fault Status RegisterReading CP15 Register 5 returns the value of theFault Status Register (FSR). The FSRcontains the source of the last fault.Note: Only the bottom 9 bits are returned. The upper 23 bits are Unpredictable.The FSR indicates the domain and type of access being attempted when an abort occurred:Bit 8 This is always read as zero. Bit 8 is ignored on writes.Bits [7:4] These specify which of the 16 domains (D15-D0) was being accessedwhen a fault occurred.Bits [3:1] These indicate the type of access being attempted.The encoding of these bits is shown inFault address and fault status registers on page 7-16.The FAR is only updated on data faults. There is no update on prefetch faults.Writing to CP15 Register 5 sets the FSR to the value of the data written. This is useful whena debugger has to restore the value of the FSR. The upper 24 bits written Should Be Zero.The CRm and opcode_2 fields Should Be Zero when reading or writing CP15 Register 5. FaultStatus Register format is shown in Figure 3-8.Figure 3-8 Fault Status Register format31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D031 30 09 08 07 06 04 03 00UNP/SBZ 0 Domain Status
