7: Memory Management Unit7-4 EPSON ARM720T CORE CPU MANUAL7.3 Address translationThe MMU translates VAs generated by the CPU core, and by CP15 register c13, into physicaladdresses to access external memory. It also derives and checks the access permission, usingthe TLB.The MMU table walking hardware is used to add entries to the TLB. The translationinformation, that comprises both the address translation data and the access permission data,resides in a translation table located in physical memory. The MMU provides the logic for youto traverse this translation table and load entries into the TLB.There are one or two stages in the hardware table walking, and permission checking, process.The number of stages depends on whether the address is marked as a section-mapped accessor a page-mapped access.There are three sizes of page-mapped accesses and one size of section-mapped access. Thepage-mapped accesses are for:• large pages• small pages• tiny pages.The translation process always starts out in the same way, with a level one fetch. Asection-mapped access requires only a level one fetch, but a page-mapped access requires asubsequent level two fetch.7.3.1 Translation Table Base RegisterThe hardware translation process is initiated when the TLB does not contain a translation forthe requested MVA. TheTranslation Table Base register points to the base address of a tablein physical memory that contains section or page descriptors, or both. The 14 low-order bits ofthe Translation Table Base Register are set to zero on a read, and the table must reside on a16KB boundary. Figure 7-1 shows the format of the Translation Table Base Register.Figure 7-1 Translation Table Base Register31 14 13 0Translation table base
