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Fujitsu MB86R02 manuals
MB86R02
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- MB86R02 'Jade-D' Hardware Manual
- block diagram
- outline of each functional block
- Remap Boot Controller (RBC)
- function summary of the blocks
- package dimensions
- pin assignment
- pin assignment table
- pin functional description
- system configuration
- memory map of lsi
- register access
- cpu (arm926ej-s core)
- configuration of arm926ej-s and etm
- clock reset generator (crg)
- location in the device
- INITRAM control
- clock generation
- register list
- pll control register (crpr)
- watchdog timer control register (crwr)
- reset/standby control register (crsr)
- clock divider control register a (crda)
- clock divider control register b (crdb)
- ahb (a) bus clock gate control register (crha)
- apb (a) bus clock gate control register (crpa)
- reserved control register (crpb)
- ahb (b) bus clock gate control register (crhb)
- arm core clock gate control register (cram)
- clock selector control register (csel)
- spread spectrum clock generator (sscg)
- Software Interface
- Global Address
- Processing Mode
- Parameter setting for SSCG-speed of 20KHz
- Parameter setting for SSCG-speed of 35KHz
- Control Flow
- Overview
- Features
- Registers
- CHIP ID register (CCID)
- Soft reset register (CSRST)
- Interrupt status register (CIST)
- Interrupt status mask register (CISTM)
- GPIO interrupt status register (CGPIO_IST)
- GPIO interrupt polarity setting register (CGPIO_IP)
- AXI bus wait cycle set register (CAXI_BW)
- AXI priority setting register (CAXI_PS)
- Multiplex mode setting register (CMUX_MD)
- External pin status register (CEX_PIN_ST)
- MediaLB set register (CMLB)
- MBUS2AXU set register (CMBUS)
- Mode switch register like endian etc. (CBSC)
- DDR2 Interface reset control register (CDCRC)
- Soft reset register 0 for macro (CMSR0)
- Soft reset register 1 for macro (CMSR1)
- Soft reset register 2 for macro (CMSR2)
- initram control
- Interrupt Request Controller (IRC)
- interrupt map
- External Interrupt Controller (EXIRC)
- Block diagram
- Register
- External interrupt enable register (EIENB)
- External interrupt request register (EIREQ)
- External interrupt level register (EILVL)
- Operation
- External Bus Interface
- Related pin
- SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4)
- SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4)
- SRAM/Flash area register 0/2/4 (MCFAREA0/2/4)
- Memory controller error register (MCERR)
- Connection example
- Example of access waveform
- Low-speed device interface function
- Endian and byte lane to each access
- Embedded SRAM
- DDR2 Controller
- Supply Clock
- DRAM initialization control register (DRIC)
- DRAM initialization command register [1] (DRIC1)
- DRAM CTRL ADD register (DRCA)
- DRAM control mode register (DRCM)
- DRAM CTRL SET TIME1 Register (DRCST1)
- DRAM CTRL SET TIME2 register (DRCST2)
- DRAM CTRL REFRESH register (DRCR)
- DRAM CTRL FIFO register (DRCF)
- AXI setting register (DRASR)
- DRAM IF MACRO SETTING DLL register (DRIMSD)
- DRAM ODT SETTING register (DROS)
- IO buffer setting ODT1 (DRIBSODT1)
- IO buffer setting OCD (DRIBSOCD)
- IO buffer setting OCD2 (DRIBSOCD2)
- ODT auto bias adjust register (DROABA)
- ODT bias select register (DROBS)
- IO monitor register 1 (DRIMR1)
- IO monitor register 3 (DRIMR3)
- OCD impedance setting register 1 (DROISR1)
- DRAM Initialization Sequence
- DRAM Initialization Procedure
- SDRAM Initialization Procedure
- OCD Adjustment Procedure
- ODT Setting Procedure
- Timer (TIMER)
- DMA Controller (DMAC)
- Related pins
- Register list
- DMA configuration register (DMACR)
- DMA configuration A register (DMACAx)
- DMA configuration B register (DMACBx)
- DMAC source address register (DMACSAx)
- DMAC destination address register (DMACDAx)
- Transfer modes
- timing chart
- Limitations with I2S DMA
- Burst transfer
- Demand transfer
- Beat transfer
- Increment and lap transfer
- Channel priority control
- Rotate priority
- Retry, split, and error
- Error
- DMAC Configuration Examples
- DMA start in all channels (in demand transfer mode)
- Host Interface
- Function
- Read Access
- Interrupt
- External Interfaces
- Data Formats
- Application Notes
- Handling of irregular operating conditions
- APIX® Interface
- Jade-D Restrictions
- Format of Register Description
- Register Summary
- Register Description
- Description of APIX Ashell and APIX PHY configuration bytes
- GPIO Interface Timing of Sideband Uplink and Downlink
- Use cases
- Use case 2
- Application Notes for PCB Designers
- Graphics Display Controller (GDC)
- Functional Overview
- Video capture function
- D Drawing
- Special effects
- Others
- Graphics Memory
- Configuration
- Data Format
- Frame Management
- Display Controller
- Display Function
- Overlay
- Display parameters
- Display position control
- Display Color
- YCbCr Color (16 bits/pixel)
- Cursor
- Interlace display
- Programmable YCbCr/RGB conversion for L1-layer display
- DCLKO shift
- Parallel Dual Display
- Multiplex Dual Display
- Output Signal Control
- Display Clock and Timing
- Video output limitation
- Video Capture
- Input Port Selection
- Video Buffer
- Synchronization Control
- Interlaced Display
- Scaling
- Flow of image processing
- External video signal input conditions
- RGB input format
- Input Operation
- Conversion Operation
- Display Controller / Video Capture Register Summary
- Video capture registers
- Explanation of Local Memory Registers
- Common control register
- Display control register
- Timing Diagrams
- Interlace video mode
- Composite synchronous signal
- Geometry Engine
- Model-view-projection (MVP) transformation
- View port transformation (NDC→DC coordinate transformation)
- Back face culling
- Setup processing
- Drawing Processing
- Texture coordinates
- Figure Drawing
- Drawing parameters
- Anti-aliasing function
- Bit Map Processing
- Texture Mapping
- Texture Wrapping
- Filtering
- Texture blending
- Rendering
- Logic operation
- Drawing Attributes
- Texture attributes
- BLT attributes
- Broken line pattern
- Edging
- Interpolation of bold line joint
- Shadowing
- Header format
- Geometry Commands
- Explanation of geometry commands
- Rendering Commands
- Details of rendering commands
- Drawing Engine / Geometry Engine Register summary
- Geometry Engine register list
- Drawing control registers
- Drawing mode registers
- Triangle drawing registers
- Line drawing registers
- Pixel drawing registers
- Blt registers
- High-speed 2D line drawing registers
- High-speed 2D triangle drawing registers
- Geometry control register
- Geometry mode registers
- Display list FIFO registers
- Display List DMA contol registers
- Interrupt registers
- Color Lookup Table (CLUT)
- Limitations
- Dither Unit
- Position
- Timing chart
- Initialization procedure
- Signature Generator (SIG)
- Signature A: CRC-32 Signature
- Processing Flow
- Example Control Flow
- Signature Generation with every incoming frame
- Cyclic Signature Generation with every incoming frame, limiting read accesses
- Timing Controller (TCON)
- Processing Algorithm
- SW Reset
- Timing Signal Module (TSIG)
- Inversion Signal Generation
- Bypass-Mode
- AC Characteristics
- Application Note
- Run-Length Decompression (RLD)
- Feature List
- Input Data Format
- Output Data Format
- Processing Modes
- AHBMTransferWidth Setup
- General-Purpose Input/Output Port (GPIO)
- Port data register 0-2 (GPDR0-2)
- Data direction register 0-2 (GPDDR0-2)
- Direction control
- Pulse Width Modulator (PWM)
- Clock Supply
- PWMx base clock register (PWMxBCR)
- PWMx pulse width register (PWMxTPR)
- PWMx phase register (PWMxPR)
- PWMx duty register (PWMxDR)
- PWMx status register (PWMxCR)
- PWMx start register (PWMxSR)
- PWMx current count register (PWMxCCR)
- PWMx interrupt register (PWMxIR)
- Example of setting a register
- A/D Converter
- Channel mapping table
- Analog pin equivalent circuit
- Format of Register Descriptions
- ADCx data register (ADCxDATA)
- ADCx clock selection register (ADCxCKSEL)
- ADCx status register (ADCxSTATUS)
- Basic operation flow
- Serial Audio Interface (I2S)
- Description format of registers
- I2SxRXFDAT register
- I2SxTXFDAT register
- I2SxCNTREG register
- I2SxMCR0REG register
- I2SxMCR1REG register
- I2SxMCR2REG register
- I2SxOPRREG register
- I2SxSRST register
- I2SxINTCNT register
- I2SxSTATUS register
- I2SxDMAACT register
- Outline
- Transfer start, stop, and malfunction
- Frame construction
- sub frame construction
- Bit alignment
- FIFO construction and description
- UART Interface
- Reception FIFO register (URTxRFR)
- Interrupt enable register (URTxIER)
- Interrupt ID register (URTxIIR)
- FIFO control register (URTxFCR)
- Line control register (URTxLCR)
- Modem control register (URTxMCR)
- Line status register (URTxLSR)
- Modem status register (URTxMSR)
- Divider latch register (URTxDLL&URTxDLM)
- UART operation
- Example of transfer procedure
- Example of reception procedure
- Basic transmission operation
- Basic reception operation
- Line status
- Character time-out interrupt
- I2C Bus Interface
- Block functions
- Bus status register (I2CxBSR)
- Bus control register (I2CxBCR)
- Clock control register (I2CxCCR)
- Address register (I2CxADR)
- Data register (I2CxDAR)
- Two bus control registers (I2CxBC2R)
- Expansion CS register (I2CxECSR)
- Bus clock frequency register (I2CxBCFR)
- Start condition
- Stop condition
- Addressing
- Synchronous arbitration of SCL
- Arbitration
- Acknowledge/Negative acknowledge
- Bus error
- Initialization
- One byte transfer from master to slave
- One byte transfer from slave to master
- Resume from bus error
- Interrupt process and wait request operation to master
- Serial Peripheral Interface (SPI)
- Transition state
- SPI control register (SPInCR)
- SPI slave control register (SPInSCR)
- SPI data register (SPInDR)
- SPI status register (SPInSR)
- Setup procedure flow
- CAN Interface (CAN)
- MediaLB Interface
- SD Memory Controller (SDMC)
- Electrical Characteristics
- Recommended Operating Conditions
- Precautions at Power On
- Power On Reset
- DC Characteristics
- V Standard CMOS I/O V-I Characteristic (Driving Capability 1)
- V Standard CMOS I/O V-I Characteristic (Driving Capability 2)
- V Standard CMOS I/O V-I Characteristics (Driving Capability 3)
- DDR2SDRAM IF I/O (SSTL_18)
- I2C Bus Fast Mode I/O
- I2C IO V-1 Characteristic Figure
- Memory Controller Signal Timing
- DDR2SDRAM Interface
- DDR2SDRAM Interface Timing Diagram
- GPIO Signal Timing
- PWM Signal Timing
- GDC Display Signal Timing
- Output Signal
- TCON active Display Timing DISP0 Interface
- RSDS Characteristics
- I2S Signal Timing
- UART Signal Timing
- I2C Bus Timing
- SPI Signal Timing
- CAN Signal Timing
- MediaLB Signal Timing
- MediaLB AC Spec Type B
- SD Signal Timing
- ETM9 Trace Port Signal Timing
- EXIRC Signal Timing
- Apix Characteristics
- Transmitter De-emphasis
- OSC Characteristics
- Multiplex (1)
- PU/PD added
- SSCG (Spread-Spectrum Modulation)
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