Application NoteMB86R02 ‘Jade-D’EMI Optimization using SSCG© Fujitsu Microelectronics Europe GmbHVersion 1.30 1

Fujitsu MB86R02 Jade-D Application Note

MB86R02 'Jade-D' Hardware Manual

block diagram

outline of each functional block

Remap Boot Controller (RBC)

function summary of the blocks

package dimensions

pin assignment

pin assignment table

pin functional description

system configuration

memory map of lsi

register access

cpu (arm926ej-s core)

configuration of arm926ej-s and etm

clock reset generator (crg)

location in the device

INITRAM control

clock generation

register list

pll control register (crpr)

watchdog timer control register (crwr)

reset/standby control register (crsr)

clock divider control register a (crda)

clock divider control register b (crdb)

ahb (a) bus clock gate control register (crha)

apb (a) bus clock gate control register (crpa)

reserved control register (crpb)

ahb (b) bus clock gate control register (crhb)

arm core clock gate control register (cram)

clock selector control register (csel)

spread spectrum clock generator (sscg)

Software Interface

Global Address

Processing Mode

Parameter setting for SSCG-speed of 20KHz

Parameter setting for SSCG-speed of 35KHz

Control Flow

Overview

Features

Registers

CHIP ID register (CCID)

Soft reset register (CSRST)

Interrupt status register (CIST)

Interrupt status mask register (CISTM)

GPIO interrupt status register (CGPIO_IST)

GPIO interrupt polarity setting register (CGPIO_IP)

AXI bus wait cycle set register (CAXI_BW)

AXI priority setting register (CAXI_PS)

Multiplex mode setting register (CMUX_MD)

External pin status register (CEX_PIN_ST)

MediaLB set register (CMLB)

MBUS2AXU set register (CMBUS)

Mode switch register like endian etc. (CBSC)

DDR2 Interface reset control register (CDCRC)

Soft reset register 0 for macro (CMSR0)

Soft reset register 1 for macro (CMSR1)

Soft reset register 2 for macro (CMSR2)

initram control

Interrupt Request Controller (IRC)

interrupt map

External Interrupt Controller (EXIRC)

Block diagram

Register

External interrupt enable register (EIENB)

External interrupt request register (EIREQ)

External interrupt level register (EILVL)

Operation

External Bus Interface

Related pin

SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4)

SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4)

SRAM/Flash area register 0/2/4 (MCFAREA0/2/4)

Memory controller error register (MCERR)

Connection example

Example of access waveform

Low-speed device interface function

Endian and byte lane to each access

Embedded SRAM

DDR2 Controller

Supply Clock

DRAM initialization control register (DRIC)

DRAM initialization command register [1] (DRIC1)

DRAM CTRL ADD register (DRCA)

DRAM control mode register (DRCM)

MB86R02

Fujitsu MB86R02 Jade-D Application Note

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