16-6MB86R02 ‘Jade-D’ Hardware Manual V1.6416.3.3. Interrupt16.3.3.1. AHB slave module access error responseAn error response from the AHB bus is output to the chip control module, CCNT. In addition, anerror response is written to the STATUS byte and the host CPU is immediately notified. TheRxRDY bit (or TxRDY bit) is set to ‘1’ at the same time. The HOSTIF module itself does not havea register to maintain this information.(rea d a cces s )(wri te a cces s )Error Respo_HST_INTHost CPUHOST-IFinterruptCNTHOST INTfromAHB busCCNTstatusRegfrominternalmoduleINTStatus byteHOST DORxRDYTxRDY 1SERR 1 1 1 1"1""1""0""1""0""1"Initial:DisableFigure 16-6 InterruptWhen an error response status has been sent to the host CPU, the transaction is completed. Ifthe CCNT interrupt setting is enabled, an interrupt is generated.16.3.4. Reset RequestA software reset of MB86R02 can be executed on request by the host CPU. If the normaloperation of the MB86R02 device is no longer possible due to certain conditions, the host CPUcan use the reset request. When a reset is executed, the MB86R02 is rebooted by the CRG unit.ix_HRESETox_HST_ASRSTHost CPUHOST-IFReset reqCNTCCNTCMD byteHOST DI ABL1 ABL0 DBL2 DBL1 DBL0 R/W CNT1 CNT0"1" "0"All_soft_ResetCRGFigure 16-7 Reset request
