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Fujitsu MB86R02 Jade-D Hardware Manual Manual pdf 1 page image

Fujitsu MB86R02 Jade-D Hardware Manual

Also see for MB86R02: Application note

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. MB86R02 'Jade-D' Hardware Manual
  17. block diagram
  18. outline of each functional block
  19. Remap Boot Controller (RBC)
  20. function summary of the blocks
  21. package dimensions
  22. pin assignment
  23. pin assignment table
  24. pin functional description
  25. system configuration
  26. memory map of lsi
  27. register access
  28. cpu (arm926ej-s core)
  29. configuration of arm926ej-s and etm
  30. clock reset generator (crg)
  31. location in the device
  32. INITRAM control
  33. clock generation
  34. register list
  35. pll control register (crpr)
  36. watchdog timer control register (crwr)
  37. reset/standby control register (crsr)
  38. clock divider control register a (crda)
  39. clock divider control register b (crdb)
  40. ahb (a) bus clock gate control register (crha)
  41. apb (a) bus clock gate control register (crpa)
  42. reserved control register (crpb)
  43. ahb (b) bus clock gate control register (crhb)
  44. arm core clock gate control register (cram)
  45. clock selector control register (csel)
  46. spread spectrum clock generator (sscg)
  47. Software Interface
  48. Global Address
  49. Processing Mode
  50. Parameter setting for SSCG-speed of 20KHz
  51. Parameter setting for SSCG-speed of 35KHz
  52. Control Flow
  53. Overview
  54. Features
  55. Registers
  56. CHIP ID register (CCID)
  57. Soft reset register (CSRST)
  58. Interrupt status register (CIST)
  59. Interrupt status mask register (CISTM)
  60. GPIO interrupt status register (CGPIO_IST)
  61. GPIO interrupt polarity setting register (CGPIO_IP)
  62. AXI bus wait cycle set register (CAXI_BW)
  63. AXI priority setting register (CAXI_PS)
  64. Multiplex mode setting register (CMUX_MD)
  65. External pin status register (CEX_PIN_ST)
  66. MediaLB set register (CMLB)
  67. MBUS2AXU set register (CMBUS)
  68. Mode switch register like endian etc. (CBSC)
  69. DDR2 Interface reset control register (CDCRC)
  70. Soft reset register 0 for macro (CMSR0)
  71. Soft reset register 1 for macro (CMSR1)
  72. Soft reset register 2 for macro (CMSR2)
  73. initram control
  74. Interrupt Request Controller (IRC)
  75. interrupt map
  76. External Interrupt Controller (EXIRC)
  77. Block diagram
  78. Register
  79. External interrupt enable register (EIENB)
  80. External interrupt request register (EIREQ)
  81. External interrupt level register (EILVL)
  82. Operation
  83. External Bus Interface
  84. Related pin
  85. SRAM/Flash mode register 0/2/4 (MCFMODE0/2/4)
  86. SRAM/Flash timing register 0/2/4 (MCFTIM0/2/4)
  87. SRAM/Flash area register 0/2/4 (MCFAREA0/2/4)
  88. Memory controller error register (MCERR)
  89. Connection example
  90. Example of access waveform
  91. Low-speed device interface function
  92. Endian and byte lane to each access
  93. Embedded SRAM
  94. DDR2 Controller
  96. Supply Clock
  97. DRAM initialization control register (DRIC)
  98. DRAM initialization command register [1] (DRIC1)
  99. DRAM CTRL ADD register (DRCA)
  100. DRAM control mode register (DRCM)
  101. DRAM CTRL SET TIME1 Register (DRCST1)
  102. DRAM CTRL SET TIME2 register (DRCST2)
  103. DRAM CTRL REFRESH register (DRCR)
  104. DRAM CTRL FIFO register (DRCF)
  105. AXI setting register (DRASR)
  106. DRAM IF MACRO SETTING DLL register (DRIMSD)
  107. DRAM ODT SETTING register (DROS)
  108. IO buffer setting ODT1 (DRIBSODT1)
  109. IO buffer setting OCD (DRIBSOCD)
  110. IO buffer setting OCD2 (DRIBSOCD2)
  111. ODT auto bias adjust register (DROABA)
  112. ODT bias select register (DROBS)
  113. IO monitor register 1 (DRIMR1)
  114. IO monitor register 3 (DRIMR3)
  115. OCD impedance setting register 1 (DROISR1)
  116. DRAM Initialization Sequence
  117. DRAM Initialization Procedure
  118. SDRAM Initialization Procedure
  119. OCD Adjustment Procedure
  120. ODT Setting Procedure
  121. Timer (TIMER)
  122. DMA Controller (DMAC)
  124. Related pins
  125. Register list
  126. DMA configuration register (DMACR)
  127. DMA configuration A register (DMACAx)
  128. DMA configuration B register (DMACBx)
  129. DMAC source address register (DMACSAx)
  130. DMAC destination address register (DMACDAx)
  131. Transfer modes
  132. timing chart
  133. Limitations with I2S DMA
  134. Burst transfer
  135. Demand transfer
  136. Beat transfer
  137. Increment and lap transfer
  138. Channel priority control
  139. Rotate priority
  140. Retry, split, and error
  141. Error
  142. DMAC Configuration Examples
  143. DMA start in all channels (in demand transfer mode)
  144. Host Interface
  145. Function
  146. Read Access
  147. Interrupt
  148. External Interfaces
  149. Data Formats
  150. Application Notes
  151. Handling of irregular operating conditions
  152. APIX® Interface
  153. Jade-D Restrictions
  155. Format of Register Description
  156. Register Summary
  157. Register Description
  158. Description of APIX Ashell and APIX PHY configuration bytes
  159. GPIO Interface Timing of Sideband Uplink and Downlink
  161. Use cases
  162. Use case 2
  163. Application Notes for PCB Designers
  164. Graphics Display Controller (GDC)
  165. Functional Overview
  166. Video capture function
  167. D Drawing
  169. Special effects
  170. Others
  171. Graphics Memory
  172. Configuration
  173. Data Format
  174. Frame Management
  175. Display Controller
  176. Display Function
  177. Overlay
  178. Display parameters
  179. Display position control
  180. Display Color
  181. YCbCr Color (16 bits/pixel)
  182. Cursor
  183. Interlace display
  184. Programmable YCbCr/RGB conversion for L1-layer display
  185. DCLKO shift
  186. Parallel Dual Display
  187. Multiplex Dual Display
  188. Output Signal Control
  189. Display Clock and Timing
  190. Video output limitation
  191. Video Capture
  192. Input Port Selection
  193. Video Buffer
  194. Synchronization Control
  195. Interlaced Display
  196. Scaling
  197. Flow of image processing
  198. External video signal input conditions
  199. RGB input format
  200. Input Operation
  201. Conversion Operation
  202. Display Controller / Video Capture Register Summary
  203. Video capture registers
  204. Explanation of Local Memory Registers
  205. Common control register
  206. Display control register
  208. Timing Diagrams
  209. Interlace video mode
  210. Composite synchronous signal
  211. Geometry Engine
  212. Model-view-projection (MVP) transformation
  213. View port transformation (NDC→DC coordinate transformation)
  214. Back face culling
  216. Setup processing
  217. Drawing Processing
  218. Texture coordinates
  219. Figure Drawing
  220. Drawing parameters
  221. Anti-aliasing function
  222. Bit Map Processing
  223. Texture Mapping
  224. Texture Wrapping
  225. Filtering
  226. Texture blending
  227. Rendering
  228. Logic operation
  229. Drawing Attributes
  230. Texture attributes
  231. BLT attributes
  232. Broken line pattern
  233. Edging
  234. Interpolation of bold line joint
  235. Shadowing
  236. Header format
  237. Geometry Commands
  238. Explanation of geometry commands
  239. Rendering Commands
  240. Details of rendering commands
  241. Drawing Engine / Geometry Engine Register summary
  242. Geometry Engine register list
  243. Drawing control registers
  244. Drawing mode registers
  245. Triangle drawing registers
  246. Line drawing registers
  247. Pixel drawing registers
  248. Blt registers
  249. High-speed 2D line drawing registers
  250. High-speed 2D triangle drawing registers
  251. Geometry control register
  252. Geometry mode registers
  253. Display list FIFO registers
  254. Display List DMA contol registers
  255. Interrupt registers
  256. Color Lookup Table (CLUT)
  258. Limitations
  259. Dither Unit
  260. Position
  261. Timing chart
  263. Initialization procedure
  264. Signature Generator (SIG)
  265. Signature A: CRC-32 Signature
  269. Processing Flow
  270. Example Control Flow
  271. Signature Generation with every incoming frame
  272. Cyclic Signature Generation with every incoming frame, limiting read accesses
  273. Timing Controller (TCON)
  275. Processing Algorithm
  276. SW Reset
  277. Timing Signal Module (TSIG)
  278. Inversion Signal Generation
  279. Bypass-Mode
  280. AC Characteristics
  282. Application Note
  284. Run-Length Decompression (RLD)
  285. Feature List
  286. Input Data Format
  287. Output Data Format
  290. Processing Modes
  291. AHBMTransferWidth Setup
  292. General-Purpose Input/Output Port (GPIO)
  295. Port data register 0-2 (GPDR0-2)
  296. Data direction register 0-2 (GPDDR0-2)
  297. Direction control
  298. Pulse Width Modulator (PWM)
  299. Clock Supply
  301. PWMx base clock register (PWMxBCR)
  302. PWMx pulse width register (PWMxTPR)
  303. PWMx phase register (PWMxPR)
  304. PWMx duty register (PWMxDR)
  305. PWMx status register (PWMxCR)
  306. PWMx start register (PWMxSR)
  307. PWMx current count register (PWMxCCR)
  308. PWMx interrupt register (PWMxIR)
  309. Example of setting a register
  310. A/D Converter
  312. Channel mapping table
  313. Analog pin equivalent circuit
  315. Format of Register Descriptions
  316. ADCx data register (ADCxDATA)
  317. ADCx clock selection register (ADCxCKSEL)
  318. ADCx status register (ADCxSTATUS)
  319. Basic operation flow
  320. Serial Audio Interface (I2S)
  324. Description format of registers
  325. I2SxRXFDAT register
  326. I2SxTXFDAT register
  327. I2SxCNTREG register
  328. I2SxMCR0REG register
  329. I2SxMCR1REG register
  330. I2SxMCR2REG register
  331. I2SxOPRREG register
  332. I2SxSRST register
  333. I2SxINTCNT register
  334. I2SxSTATUS register
  335. I2SxDMAACT register
  336. Outline
  337. Transfer start, stop, and malfunction
  338. Frame construction
  339. sub frame construction
  340. Bit alignment
  341. FIFO construction and description
  342. UART Interface
  345. Reception FIFO register (URTxRFR)
  346. Interrupt enable register (URTxIER)
  347. Interrupt ID register (URTxIIR)
  348. FIFO control register (URTxFCR)
  349. Line control register (URTxLCR)
  350. Modem control register (URTxMCR)
  351. Line status register (URTxLSR)
  352. Modem status register (URTxMSR)
  353. Divider latch register (URTxDLL&URTxDLM)
  354. UART operation
  355. Example of transfer procedure
  356. Example of reception procedure
  357. Basic transmission operation
  358. Basic reception operation
  359. Line status
  360. Character time-out interrupt
  361. I2C Bus Interface
  363. Block functions
  366. Bus status register (I2CxBSR)
  367. Bus control register (I2CxBCR)
  368. Clock control register (I2CxCCR)
  369. Address register (I2CxADR)
  370. Data register (I2CxDAR)
  371. Two bus control registers (I2CxBC2R)
  372. Expansion CS register (I2CxECSR)
  373. Bus clock frequency register (I2CxBCFR)
  374. Start condition
  375. Stop condition
  376. Addressing
  377. Synchronous arbitration of SCL
  378. Arbitration
  379. Acknowledge/Negative acknowledge
  380. Bus error
  381. Initialization
  382. One byte transfer from master to slave
  383. One byte transfer from slave to master
  384. Resume from bus error
  385. Interrupt process and wait request operation to master
  386. Serial Peripheral Interface (SPI)
  388. Transition state
  390. SPI control register (SPInCR)
  391. SPI slave control register (SPInSCR)
  392. SPI data register (SPInDR)
  393. SPI status register (SPInSR)
  394. Setup procedure flow
  395. CAN Interface (CAN)
  397. MediaLB Interface
  399. SD Memory Controller (SDMC)
  400. Electrical Characteristics
  401. Recommended Operating Conditions
  402. Precautions at Power On
  403. Power On Reset
  404. DC Characteristics
  405. V Standard CMOS I/O V-I Characteristic (Driving Capability 1)
  406. V Standard CMOS I/O V-I Characteristic (Driving Capability 2)
  407. V Standard CMOS I/O V-I Characteristics (Driving Capability 3)
  408. DDR2SDRAM IF I/O (SSTL_18)
  409. I2C Bus Fast Mode I/O
  410. I2C IO V-1 Characteristic Figure
  411. Memory Controller Signal Timing
  412. DDR2SDRAM Interface
  413. DDR2SDRAM Interface Timing Diagram
  414. GPIO Signal Timing
  415. PWM Signal Timing
  416. GDC Display Signal Timing
  417. Output Signal
  418. TCON active Display Timing DISP0 Interface
  419. RSDS Characteristics
  420. I2S Signal Timing
  421. UART Signal Timing
  422. I2C Bus Timing
  423. SPI Signal Timing
  424. CAN Signal Timing
  425. MediaLB Signal Timing
  426. MediaLB AC Spec Type B
  427. SD Signal Timing
  428. ETM9 Trace Port Signal Timing
  429. EXIRC Signal Timing
  430. Apix Characteristics
  431. Transmitter De-emphasis
  432. OSC Characteristics
  433. Multiplex (1)
  434. PU/PD added
  435. SSCG (Spread-Spectrum Modulation)
Fujitsu MB86R02 Jade-D Hardware Manual Manual pdf 1 page image
MB86R02 ‘Jade-D’ Hardware Manual V1.64MB86R02 ‘Jade-D’Graphics ControllerHardware ManualFujitsu Semiconductor Europe GmbHRelease 1.64 (amended)(17.09.2013 13:11)This document is subject to changesand corrections without prior warning
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