TXZ+ FamilyTMPM4M Group(1)Clock Control and Operation Mode2022-06-24Rev. 1.135 / 64Bit Bit Symbol After reset Type Function24 IPMENA24 0 R/WClock enable of UART ch3 (TSEL24)0: Clock stop1: Clock supply23 IPMENA23 0 R/WClock enable of UART ch2 (TSEL23)0: Clock stop1: Clock supply22 IPMENA22 0 R/WClock enable of UART ch1 (TSEL22)0: Clock stop1: Clock supply21 IPMENA21 1 R/WClock enable of UART ch0 (TSEL21)0: Clock stop1: Clock supply20 IPMENA20 0 R/WClock enable of TSPI ch1 (TSEL20)0: Clock stop1: Clock supply19 IPMENA19 0 R/WClock enable of TSPI ch0 (TSEL19)0: Clock stop1: Clock supply18 - 0 R Read as "0"17 IPMENA17 0 R/WClock enable of PORT V0: Clock stop1: Clock supply16 IPMENA16 0 R/WClock enable of PORT U0: Clock stop1: Clock supply15 - 0 R Read as "0"14 - 0 R Read as "0"13 - 0 R Read as "0"12 IPMENA12 0 R/WClock enable of PORT N0: Clock stop1: Clock supply11 IPMENA11 0 R/WClock enable of PORT M0: Clock stop1: Clock supply10 IPMENA10 0 R/WClock enable of PORT L0: Clock stop1: Clock supply9 IPMENA09 0 R/WClock enable of PORT K0: Clock stop1: Clock supply8 IPMENA08 0 R/WClock enable of PORT J0: Clock stop1: Clock supply7 IPMENA07 0 R/WClock enable of PORT H0: Clock stop1: Clock supply6 IPMENA06 0 R/WClock enable of PORT G0: Clock stop1: Clock supply