Toshiba TXZ+ TMPM4MNFYAFG Reference Manual

TXZ+ FamilyTMPM4M Group(1)Clock Control and Operation Mode2022-06-24Rev. 1.118 / 641.2.6. System clockAn internal high speed oscillation clock or external high speed oscillation clock (connected oscillator or clockinput) can be used as a source of system clock.The system clock consists of "High speed system clock (fsysh)(maximum 160MHz )" for high speed operationand "Middle speed system clock (fsysm)(maximum 80MHz)" which is generated by dividing High speed systemclock. Middle speed system clock is used by peripheral function to save power dissipation without degrading CPUperformance. The clock domains of the peripheral function can be checked in Table 1.4.High speed system clock can be generated by dividing fc using [CGSYSCR]<GEAR[2:0]> (Clock gear). AndMiddle speed system clock is generated by dividing the high speed system clock using [CGSYSCR]1:0]>. Although a setting can be changed during operation, after register writing before the clockactually changes, a time interval shown in Table 1.5 is required. The completion of the clock change should bechecked by [CGSYSCR] .Table 1.4 Clock domains of CPU and peripheralsClock domain BlockHigh speed system clock CPU, Code FLASH, Data FLASH, Boot ROM, RAM0/1, CG,INTIF(IB, IMN), CRC, RAMP(ch0)Middle speed system clockDMAC, NBDIF, SIWDT, UART, CAN, TSPI, I2C, EI2C, T32A, ADC,OPAMP, Port, A-PMD, A-ENC32, A-VE+, INTIF(IA), DNF, LVD,TRM, FLASH(SFR), OFD, RAMP(ch1) , RLM, TRGSEL, RAM2Table 1.5 Time interval for changing System clockSystem clock High speed (fsysh) Middle speed (fsysm)fsys 16 fc cycles at maximum 16 fc cycles at maximumfsys/2 - 32 fc cycles at maximumfsys/4 - 64 fc cycles at maximumNote1: The clock gear and the system clock should not be changed while the peripheral function such as thetimer/counter is operating.Note2: An access between High speed system clock domain and Middle speed system clock domain cannot bedone when the system clock is changing.The table below shows the example of operation frequency by the clock gear ratio (1/1 to 1/16) to the frequency fcset up with oscillation frequency, a PLL multiplication value, etc.Table 1.6 Example of operation frequencyExternalOscillation(MHz)ExternalClockinput(MHz)Built-inoscillationIHOSC1(MHz)PLLMultiplicationvalue(after dividing)MaximumFrequency(fc)(MHz)Operation frequency (MHz)by the clock gear ratioPLL=ONOperation frequency (MHz)by the clock gear ratioPLL=OFF1/1 1/2 1/4 1/8 1/16 1/1 1/2 1/4 1/8 1/166 6 - 26.66 159.94 159.94 79.97 39.99 19.99 10.00 6 3 1.5 - -8 8 - 20 160 160 80 40 20 10 8 4 2 1 -10 10 10 16 160 160 80 40 20 10 10 5 2.5 1.25 -12 12 - 13 156 156 78 39 19.5 9.75 12 6 3 1.5 -