– aa is the SDRAM speed grade– m is the DIMM type– E = Unbuffered DIMM (UDIMM), x64 primary + 8 bit ECC module data bus– L = Load Reduced DIMM (LRDIMM), x64 primary + 8 bit ECC module data bus– R = Registered DIMM (RDIMM), x64 primary + 8 bit ECC module data bus– U = Unbuffered DIMM (UDIMM) with no ECC (x64-bit primary data bus)– cc is the reference design file used for this design– d is the revision number of the reference design used– bb is the JEDEC SPD Revision Encoding and Additions level used on this DIMMThe following illustration shows the location of the DIMM connectors on the system board.Figure 32. The location of the DIMM connectors on the system boardInstallation orderMemory modules must be installed in a specific order based on the memory configuration that youimplement on your node.The following memory configurations are available:• “Memory mirroring population sequence” on page 47• “Memory rank sparing population sequence” on page 47• “Independent memory mode population sequence” on page 46For information about memory modes, see “Memory configuration” on page 71Independent memory mode population sequenceTable 11. DIMM installation sequence (Independent mode/normal mode)2 processors installedNumber of DIMM installed Installation sequence (connectors)2 4, 124 4, 5, 12, 136 1, 4, 5, 9, 12, 138 1, 4, 5, 8, 9, 12, 13, 1646 ThinkSystem SD650 Dual Node DWC Tray and NeXtScale n1200 DWC Enclosure Setup Guide