5-186 F60 Feeder Protection System GE Multilin5.6 CONTROL ELEMENTS 5 SETTINGS5The algorithm is in “Normal” state when it detects no abnormal activity on the power system. While in the “Normal” state,any one of several power system events (a high output of the Expert Arc Detector, a significant loss of load, or a Hi-Z over-current) cause the algorithm to move to the “Coordination Timeout” state, where it remains for the time specified by the OCPROTECTION COORD TIMEOUT setting. Following this interval, the algorithm moves into its “Armed” state. The criteria fordetecting arcing or a downed conductor are:1. the Expert Arc Detector Algorithm's output reaches a high level enough times, and2. its high level was last reached when the algorithm's state was “Armed”.The “Arcing Sensitivity” setting determines what level constitutes a “high” output from the Expert Arc Detector Algorithm,and the number that constitutes what “enough times” means. If these criteria are met, the algorithm temporarily moves toeither the “Arcing” state or the “Downed Conductor” state, the difference being determined by whether or not there was aTable 5–22: HI-Z SPECIFIC DATA# NAME DESCRIPTION0 EadCounts Total number of EAD counts for the phase1 ArcConfidence ArcConfidence for the phase2 AccumArcConf Accumulated ArcConfidence for the phase3 RmsCurrent The 2-cycle RMS current for the phase4 HighROC Flag indicating a high rate of change was detected5 IOC Flag indicating an instantaneous 2-cycle overcurrent was detected6 LossOfLoad Flag indicating a loss of load was detected7 EadZeroed Flag indicating that this phase’s EAD table was cleared8 HighZArmed Flag indicating that this phase is armed for a high-Z detection9 VoltageDip Flag indicating that a voltage dip was detected on this phase10 HighEad Flag indicating that a high arc confidence occurred on this phase11 ArcBurst Flag indicating that an arc burst was identified on this phase12 VDisturbanceCc Cycle-to-cycle voltage disturbance13 VDisturbanceAbs Absolute voltage disturbance14 HarmonicRestraint Harmonic RestraintTable 5–23: HI-Z CAPTURE DATA# NAME DESCRIPTION1 StatusMask Bit-mask of the algorithm state (16 bits)BIT_ARCINGBIT_DOWNED_CONDBIT_ARC_TRENDBIT_PHASE_ABIT_PHASE_BBIT_PHASE_CBIT_PHASE_NBIT_IOC_ABIT_IOC_BBIT_IOC_CBIT_IOC_NBIT_LOL_ABIT_LOL_BBIT_LOL_CBIT_I_DISTURBANCEBIT_V_DISTURBANCE2 AlgorithmState Present value of the High-Z output state machine: Normal = 0, Coordination Timeout = 1,Armed = 2, Arcing = 5, Downed Conductor = 93 EadZeroedFlag Flag indicating the EAD table was cleared4 SpectralFlag Flag indicating the Spectral algorithm has found a match5 ThreePhaseFlag Flag indicating a three phase event was detected6 PhaseInfo[4] Phase specific information for the three phase currents and the neutral (see table below)
