Epson S1C31D50 Technical Manual

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2 POWER SUPPLY, RESET, AND CLOCKS2-16 Seiko Epson Corporation S1C31D50/D51 TECHNICAL MANUAL(Rev. 2.00)CLG System Clock Control RegisterRegister name Bit Bit name Initial Reset R/W RemarksCLGSCLK 15 WUPMD 0 H0 R/WP –14 – 0 – R13–12 WUPDIV[1:0] 0x0 H0 R/WP11–10 – 0x0 – R9–8 WUPSRC[1:0] 0x0 H0 R/WP7–6 – 0x0 – R5–4 CLKDIV[1:0] 0x2 H0 R/WP3–2 – 0x0 – R1–0 CLKSRC[1:0] 0x0 H0 R/WPBit 15 WUPMDThis bit enables the SYSCLK switching function at wake-up.1 (R/WP): Enable0 (R/WP): DisableWhen the CLGSCLK.WUPMD bit = 1, setting values of the CLGSCLK.WUPSRC[1:0] bits and theCLGSCLK.WUPDIV[1:0] bits are loaded to the CLGSCLK.CLKSRC[1:0] bits and the CLGSCLK.CLKDIV[1:0] bits, respectively, at wake-up from SLEEP mode to switch SYSCLK. When the CLG-SCLK.WUPMD bit = 0, the CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are notaltered at wake-up.Bit 14 ReservedBits 13–12 WUPDIV[1:0]These bits select the SYSCLK division ratio for resetting the CLGSCLK.CLKDIV[1:0] bits at wake-up.This setting is ineffective when the CLGSCLK.WUPMD bit = 0.Bits 11–10 ReservedBits 9–8 WUPSRC[1:0]These bits select the SYSCLK clock source for resetting the CLGSCLK.CLKSRC[1:0] bits at wake-up.When a currently stopped clock source is selected, it will automatically start oscillating or clock inputat wake-up. However, this setting is ineffective when the CLGSCLK.WUPMD bit = 0.Table 2.6.2 SYSCLK Clock Source and Division Ratio Settings at Wake-upCLGSCLK.WUPDIV[1:0] bitsCLGSCLK.WUPSRC[1:0] bits0x0 0x1 0x2 0x3IOSCCLK OSC1CLK OSC3CLK EXOSCCLK0x3 1/8 Reserved 1/16 Reserved0x2 1/4 Reserved 1/8 Reserved0x1 1/2 1/2 1/2 Reserved0x0 1/1 1/1 1/1 1/1Bits 7–6 ReservedBits 5–4 CLKDIV[1:0]These bits set the division ratio of the clock source to determine the SYSCLK frequency.Bits 3–2 ReservedBits 1–0 CLKSRC[1:0]These bits select the SYSCLK clock source.When a currently stopped clock source is selected, it will automatically start oscillating or clock input.