Epson S1C31D50 Technical Manual

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PREFACES1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation i(Rev. 2.00)PrefaceThis is a technical manual for designers and programmers who develop a product using the S1C31D50/D51. Thisdocument describes the functions of the IC, embedded peripheral circuit operations, and their control methods.Notational conventions and symbols in this manualRegister addressPeripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” inthe “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.Register and control bit namesIn this manual, the register and control bit names are described as shown below to distinguish from signaland pin names.XXX register: Represents a register including its all bits.XXX.YYY bit: Represents the one control bit YYY in the XXX register.XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.Register table contents and symbolsInitial: Value set at initializationReset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” inthe “Power Supply, Reset, and Clocks” chapter.R/W: R = Read only bitW = Write only bitWP = Write only bit with a write protection using the SYSPROT.PROT[15:0] bitsR/W = Read/write bitR/WP = Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits(reserved): Reserved bit. Do not alter from the initial value.Control bit read/write valuesThis manual describes control bit values in a hexadecimal notation except for one-bit values (and exceptwhen decimal or binary notation is required in terms of explanation). The values are described as shownbelow according to the control bit width.1 bit: 0 or 12 to 4 bits: 0x0 to 0xf5 to 8 bits: 0x00 to 0xff9 to 12 bits: 0x000 to 0xfff13 to 16 bits: 0x0000 to 0xffffDecimal: 0 to 9999...Binary: 0b0000... to 0b1111...Channel numberMultiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheralcircuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.If there is a channel that has different functions from others, the channel number is specified clearly.Example) T16_nCTL register of the 16-bit timerIf one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL onlyIf two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTLFor the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the“Overview” chapter.Low power modeThis manual describes the low power modes as HALT mode and SLEEP mode. These terms refer to sleepmode and deep sleep mode in the Cortex®-M0+ processor, respectively.