Basler A500k User Manual

Also see for A500k: Wood burning fireplace User manual

Contents

Basler A500k User Manual Manual pdf 34 page image

Camera Interface2-20 Basler A500k SeriesPRELIMINARYThe sensor outputs 10 Bits, but the two bits output from each ADC are dropped and only 8 bits ofdata per pixel is transmitted. The digital shift function selects the bits to be dropped (see section3.8).Video Data Sequence for the A501k/kcWhen the camera is not transmitting valid data, the frame valid and line valid bits sent on eachcycle of the pixel clock will be low. The camera can acquire a frame and, at the same time, sendthe previous frame. It can also first acquire a frame and then send it. When Frame valid becomeshigh, the camera starts to send valid data:• On the pixel clock cycle where frame data transmission begins, the frame valid bit willbecome high. Five pixel clocks later, the line valid bit will become high (if AOI Starting Col-umn = 0).• On the pixel clock cycle where data transmission for line one begins, the line valid bit willbecome high. Two data streams are transmitted in parallel during this clock cycle. The firstpixel is the first pixel in the first data stream D_0. The second pixel is the first pixel in the sec-ond data stream D_1. 8 bits will contain the data for each pixel.• On the next cycle of the pixel clock, the line valid bit will be high. The third pixel is the secondpixel in the D_0 data stream. The fourth pixel is the second pixel in the D_1 data stream. 8bits will contain the data for each pixel.• On the next cycle of the pixel clock, the line valid bit will be high. The fifth pixel is the thirdpixel in the D_0 data stream. The sixth pixel is the third pixel in the D_1 data stream. 8 bitswill contain the data for each pixel.• This pattern will continue until all of the pixel data for each data stream for line one has beentransmitted. (A total of 640 cycles for the A501k/kc.)• Line valid becomes low for twenty pixel clocks.• On the pixel clock cycle where data transmission for line two begins, the line valid bit willbecome high. Two data streams are transmitted in parallel during this clock cycle. In eachdata stream, 8 bits will contain the data for the first and second pixel of line number two.• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data forthe third and fourth pixel of line number two.• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data forthe fifth and sixth pixel of line number two.• This pattern will continue until all of the pixel data for each data stream for line two has beentransmitted. (A total of 640 cycles.)• After all of the pixels in line two have been transmitted, the line valid bit will become low fortwenty cycles indicating that valid data for line two is no longer being transmitted.• The camera will continue to transmit pixel data for each line as described above until all ofthe lines in the frame have been transmitted. After all of the lines have been transmitted, the* The data sequence outlined below, along with Figures 2-9 and 2-10, describe whatis happening at the inputs to the Channel Link transmitters in the camera.Note that the timing used for sampling the data at the Channel Link receivers in theframe grabber varies from device to device. On some receivers, data must be sam-pled on the rising edge of the pixel clock (receive clock), and on others, it must besampled on the falling edge. Also, some devices are available which allow you toselect either rising edge or falling edge sampling. Please consult the data sheet forthe receiver that you are using for specific timing information.