SP605 Hardware User Guide www.xilinx.com 23UG526 (v1.1.1) February 1, 2010Detailed DescriptionFMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAGaccess to the FPGA on the basic SP605 board (without FMC expansion modules installed),as shown in Figure 1-7. When the VITA 57.1 FMC LPC expansion connector is populatedwith an expansion module that has a JTAG chain, jumper J19 must be set to connect pins2-3 in order to include the FMC expansion module's JTAG chain in the main SP605 JTAGchain.The JTAG chain can be used to program the FPGA and access the FPGA for hardware andsoftware debug.The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to theFPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allowsdebug tools such as the ChipScope® Pro Analyzer tool or a software debugger to accessthe FPGA. The iMPACT software tool can also program the BPI flash via the USB J4connection. iMPACT can download a temporary design to the FPGA through the JTAG.This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPIinterface. Through the connection made by the temporary design in the FPGA, iMPACTcan indirectly program the BPI flash from the JTAG USB J4 connector. For an overview onconfiguring the FPGA, see “Configuration Options,” page 55.7. Clock GenerationThere are three clock sources available on the SP605.Oscillator (Differential)The SP605 has one 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the boardand wired to an FPGA global clock input.• Crystal oscillator: Epson EG-2121CA-200.0000M-LHPA• PPM frequency jitter: 50 ppmReferencesSee the Epson EG-2121CA Data Sheet for more information. Search EG-2121CA at EpsonToyocom. [Ref 15]X-Ref Target - Figure 1-7Figure 1-7: VITA 57.1 FMC LPC (J2) JTAG Bypass Jumper J19UG526_07_092409J191FMC_TDI_BUFBypass FMC LPC J2 = Jumper 1-2Include FMC LPC J2 = Jumper 2-3H - 1x32SYSACE_TDI3FMC_TD0