Toshiba TC9314F Manual

TC9314F2003-07-0315Machine Language (16 bit)Inst. Gr.MnemonicSkipFunctionExplanation of Function Explanation of Operation IC(6 bit)A(2 bit)B(4 bit)C(4 bit)TMTR r, M *Test general register bitsby memory bits, then skipif all bits specified aretrueSkip if r [N (M)] all “1” 010000 DR DC RNTMFR r, M *Test general register bitsby memory bits, then skipif all bits specified arefalseSkip if r [N (M)] all “0” 010001 DR DC RNTMT M, N *Test memory bits, thenskip if all bits specifiedare trueSkip if M (N) all “1” 110101 DR DC NTMF M, N *Test memory bits, thenskip if all bits specifiedare falseSkip if M (N) all “0” 110111 DR DC NTMTN M, N *Test memory bits, thennot skip if all bitsspecified are trueSkip if M (N) not all “1” 110100 DR DC NTMFN M, N *Test memory bits, thennot skip if all bitsspecified are falseSkip if M (N) not all “0” 110110 DR DC NSKP * Skip if carry flag is set Skip if (CY) 1 111111 00 0011BIT JUDGE INSTRUCTIONSKPN * Skip if carry flag is reset Skip if (CY) 0 111111 01 0011CALL ADDR1 Call subroutine STACK m (PC) 1 andPC m ADDR1 100 ADDR1 (13 bit)RN Return to main routine PC m (STACK) 111111 10 0011SUBROUTINEINSTRUCTIONRNS * Return to main routineand skip unconditionally PC m (STACK) and skip 111111 11 0011JUMPINST.JUMP ADDR1 Jump to the addressspecified PC m ADDR1 101 ADDR1 (13 bit)SHRC M Shift memory bits to rightdirection with carry0 o (M) b3 o (M) b2 o(M) b1 o (M) b0 o (CY) 111111 DR DC 0000RORC M Rotate memory bits toright direction with carry(M) b3 o (M) b2 o(M) b1 o (M) b0 o(CY) 111111 DR DC 0001XCH M Exchange memory bitsmutually(M) b3 l (M) b0,(M) b2 l (M) b1 111111 DR DC 0110DAL ADDR2, r Load program memory inpage 0 to DATA registerDATA m [ADDR2 (r)] Pin page 0 111110 ADDR2 (6 bit) RNAt P “0” H, the conditionis CPU waiting (Soft waitmode)WAIT P At P “1” H, except forclock generator, allfunction is waiting (Hardwait mode)Wait at condition P 111111 P 0100CKSTP Clock generator stopStop clock generatoraccording to MODEcondition111111 0101OTHER INSTRUCTIONNOOP No operation 111111 1111Note 12: Among 10 bits of the program memory address assigned by DAL instruction, the lower rank of 4 bitsbecome indirect addressing based on the content of general register.DAL instruction executing time is 80 Ps. (2 machine cycles)Note 13: MVGS instruction executing time is 80 Ps. (2 machine cycles)