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Samsung S3F84B8 Design Manual
Also see for S3F84B8: User manual
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S3F84B8_ALL-IN-ONE IH COOKER_AN_REV 0.00 3 SOFTWARE IMPLEMENTATION3-43.3 INTERNAL RESOURCE ARRANGEMENT AND CONFIGURATIONTable 3-1 shows the internal resource arrangement and configuration.Table 3-1 Internal Resource Arrangement and ConfigurationModule Purpose Configuration RegistersCMP0 Synchronization Non-inverting outputDisable INTCMP0CONCMPINTP1CONCMP2 Surge protection 0.50VDD referenceNon-inverting outputEnable INTCMP1CONCMPINTP1CONCMP1 IGBT over-V protection 0.65VDD reference,Non-inverting output,Enable INTCMP2CONCMPINTP1CONOPA Current amplification On-chip mode OPACONP2CONLPWM IGBT control Co-operate with CMP0Delay TriggerAMT TriggerPWMCONPWMCCONPWMDATAH/LPWMPDATAH/LP0CONHBUZ BUZ control 1KHz output BUZCONP0CONLTA 100ms timing for1) BUZ beaming time (0.2sec for every enable)2) Display blink interval (0.5sec)3) Error warning (BUZ) after error lasts for 2sec4) Pan-on detect every 2sec5) Move pan detect every 1.5sec6) Power adjust every 0.1sec7) Check sensor status after 3min of heating upInternal modeMatch Interrupt EnableTA Internal Clock = Fosc/4096TAPSTACONTC Pulse counting for pan detection Interval modeInterrupt DisableTC clock = CMP0_OTCCONTCPSTable 3-1 shows the internal resource arrangement for IH cooker system and related registers in S3F84B8. Fordetail description of all the registers and co-operation ways of comparators and IH PWM, refer to the S3F84B8user’s manual. |
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