234DX-600/800APR 2002Edition 1.06.2.14 LAN Control CircuitLAN Controller1. LAN Controller (IC1)This conforms to IEEE 802.3 Ethernet Controller. The CPU (SC PCB) bus is directly connected and thedata interrupt is controlled by pLANINT. The 25 MHz clock is supplied by OSC 1. The LAN Controllerfor the system timing clock divides the frequency provided from OSC1. The clock signal is alsosupplied for the Manchester encoding/decoding circuit for data conversion.The LAN Controller is a mixed signal Analog/Digital device that implements the MAC and PHY portionof the CSMA/CD protocol at 10 and 100Mbps.The LAN controller contains a built in 8 KByte RAM for transmission and reception buffer.2. EEPROM (IC2)This memory stores the configuration registers and MAC (Media Access Control) address for the LANcontroller. Data is transferred to LAN controller (serial transfer) when the power is turned "On". TheMAC address for the LAN controller represents the location on the LAN.3. Filter Transformer (T1)A choke module transformer with a EMI filter. The output TX signal from the LAN controller isdifferentiated and transmitted on to the LAN via this module. Similarly, the input RX signal(differential input pair) is terminated by an externally connected 75 ohms resistor and input to the LANcontroller via this module.4. Ethernet InterfaceProvides the 10Base-T/100Base-TX Ethernet interface.FROM 4MBImage Memory(IC10)LANBPCBLANCPCBCPUV850E/MA1(IC1)SHINEDZAC000273(IC3)FROM 4MBProgram(IC9)MN86075(IC30)MODEMMN195006(I22)DAASi3021,Si3015(IC23,24)D-BUSLaser PrinterCCD PCBLineLineMemoryPageMemoryECMBufferS-DRAM 8MB(IC7)(2)Transformer(T1)LAN Controller(IC1)RJ45LINKACTIVITYINTERNET(10Base-T/100Base-TX)(1)
