112 Chapter 4Phoenix BIOS Beep CodesCode Beeps POST Routine Description02h Verify Real Mode03h Disable Non-Maskable Interrupt (NMI)04h Get CPU type06h Initialize system hardware08h Initialize chipset with initial POST values09h Set IN POST flag0Ah Initialize CPU registers0Bh Enable CPU cache0Ch Initialize caches to initial POST values0Eh Initialize I/O component0Fh Initialize the local bus IDE10h Initialize Power Management11h Load alternate registers with initial POSTvalues12h Restore CPU control word during warmboot13h Initialize PCI Bus Mastering devices14h Initialize keyboard controller16h 1-2-2-3 BIOS ROM checksum17h Initialize cache before memory autosize18h 8254 timer initialization1Ah 8237 DMA controller initialization1Ch Reset Programmable Interrupt Controller20h 1-3-1-1 Test DRAM refresh22h 1-3-1-3 Test 8742 Keyboard Controller24h Set ES segment register to 4 GB26h Enable A20 line28h Autosize DRAM29h Initialize POST Memory Manager2Ah Clear 215 KB base RAM2Ch 1-3-4-1 RAM failure on address line xxxx2Eh 1-3-4-3 RAM failure on data bits xxxx of low byteof memory bus2Fh Enable cache before system BIOSshadow30h 1-4-1-1 RAM failure on data bits xxxx of high byteof memory bus32h Test CPU bus-clock frequency33h Initialize Phoenix Dispatch Manager36h Warm start shut down38h Shadow system BIOS ROM3Ah Autosize cache
