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Abov MC96FR116C Series User Manual

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Contents
  1. REVISION HISTORY
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. MC96FR116C
  9. Ordering Information
  10. Figure 1-1 Device Nomenclature
  11. Development Tools
  12. Figure 1-3 OCD Mode Sequence
  13. Figure 1-4 OCD Interface Circuit
  14. Figure 1-5 E-PGM
  15. Figure 1-6 PGMPlusLC-II
  16. BLOCK DIAGRAM
  17. PIN CONFIGURATIONS
  18. Figure 3-2 16 QFN Pin-out of MC96FR116CU
  19. Figure 3-3 20 TSSOP Pin-out of MC96FR116CR
  20. PACKAGE DIMENSION
  21. Figure 4-2 PKG DIMENSION (16 QFN)
  22. Figure 4-3 PKG DIMENSION (20 TSSOP)
  23. PIN DESCRIPTION
  24. PORT STRUCTURES
  25. External Interrupt I/O Port
  26. REM_PP_OUT Port
  27. ELECTRICAL CHARACTERISTICS
  28. VOLTAGE DROPOUT CONVERTER(1.8V Internal regulator) CHARACTERISTICS
  29. Internal RC Oscillator CHARACTERISTICS
  30. POWER-ON RESET CHARACTERISTICS
  31. AC CHARACTERISTICS
  32. Figure 7-1 AC Timing
  33. I2C CHARACTERISTICS
  34. REM_PP_OUT PORT CHARACTERISTICS
  35. REM_OD_OUT PORT CHARACTERISTICS
  36. MEMORY
  37. IRAM
  38. Figure 8-3 Lower 128 Byte of IRAM
  39. Figure 8-4 PSW Register
  40. XRAM
  41. Registers
  42. I/O PORTS
  43. Interrupt Controller
  44. External Interrupt
  45. Interrupt Vectors
  46. Effective time of Interrupt Request
  47. Multiple Interrupts
  48. Interrupt Service Procedure
  49. Saving and Restoring General Purpose Registers
  50. Interrupt Timing
  51. Peripheral Units
  52. Basic Interval Timer (BIT)
  53. Figure 11-2 Block Diagram of BIT
  54. Watch Dog Timer (WDT)
  55. Figure 11-4 WDT Interrupt and Reset Timing
  56. TIMER/PWM
  57. Figure 11-5 Block Diagram of Timer 0,1 in 8-bit timer/counter mode
  58. Figure 11-6 Interrupt Period of Timer 0, 1
  59. Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode
  60. Figure 11-9 Block Diagram of Timer 0, 1 in 8-bit Capture mode
  61. Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode
  62. Figure 11-12 Block Diagram of Timer 0, 1 in 16-bit Capture Mode
  63. Figure 11-13 Block Diagram of Timer 1 in PWM mode
  64. Figure 11-16 Block Diagram of 16-bit Timer 2 in Output Compare or Event Counter Mode
  65. Figure 11-18 Block Diagram of Timer 2 in Carrier Counting Mode
  66. Figure 11-19 Block Diagram of Timer 3 in Output Compare or Event Counter Mode
  67. Figure 11-20 Block Diagram of Timer 3 in Capture Mode
  68. Figure 11-21 Block Diagram of Timer 3 in Carrier Counting Mode
  69. Figure 11-22 Block Diagram of Timer 3 in PWM Mode
  70. Watch Timer with event capture function (WT)
  71. Figure 11-25 Block Diagram of Watch Timer in IR capture mode
  72. IR Capture Control (IRCC)
  73. Figure 11-29 Timing Diagram of IR Learning
  74. Carrier Generator
  75. Figure 11-31 Period of Carrier signal and Remote data pulse
  76. Figure 11-32 REMOUT by CRF & ROB (In case of CEN=1, RDPE=1)
  77. Figure 11-33 REMOUT by ROB only (In case of CEN=0, RDPE=1)
  78. Key Scan
  79. UART
  80. Figure 11-36 The Block Diagram of UART
  81. Figure 11-38 The Block Diagram of Clock Generation
  82. Figure 11-39 frame format
  83. Figure 11-40 Start Bit Sampling
  84. Figure 11-41 The Sampling of Data and Parity Bit
  85. Figure 11-45 START and STOP Condition
  86. Figure 11-46 STOP or Repeated START Condition
  87. Figure 11-48 Clock Synchronization during Arbitration Procedure
  88. Figure 11-50 Formats and States in the Master Transmitter Mode
  89. Figure 11-51 Formats and States in the Master Receiver Mode
  90. Figure 11-52 Formats and States in the Slave Transmitter Mode
  91. Figure 11-53 Formats and States in the Slave Receiver Mode
  92. POWER MANAGEMENT
  93. STOP mode
  94. Figure 12-3 Wake-up from STOP mode by an interrupt
  95. BOD mode
  96. Figure 12-5 BOD mode during normal mode
  97. Figure 12-6 BOD mode during stop mode
  98. Register Map
  99. RESET
  100. Noise Canceller for External Reset Pin
  101. Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly)
  102. External RESETB Input
  103. Brown Out Detector
  104. Figure 13-8 Block Diagram of BOD
  105. On-chip Debug System
  106. Two-pin external interface
  107. Figure 14-2 10-bit transmission packets
  108. Figure 14-4 Bit transfer on the serial bus
  109. Figure 14-7 Clock synchronization during wait procedure
  110. FLASH Memory Controller
  111. Register Description
  112. Memory map
  113. Serial In-System Program Mode
  114. Security
  115. FUSE
  116. APPENDIX
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This manual is suitable for:
MC96FR116C SeriesMC96FR116CRMC96FR116CUMC96FR116CW