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MC96FR364B
Abov MC96FR364B User Manual
Abov MC96FR364B User Manual
Table of content
Contents
REVISION HISTORY
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
MC96FR364B
Ordering Information
Figure 1-1 Device Nomenclature
Development Tools
Figure 1-3 E-PGM
Figure 1-4 PGMPlusLC-II
BLOCK DIAGRAM
PIN CONFIGURATIONS
PACKAGE DIMENSION
Figure 4-1 PKG DIMENSION (28 TSSOP)
PIN DESCRIPTION
PORT STRUCTURES
External Interrupt I/O Port
REMOUT Port
ELECTRICAL CHARACTERISTICS
VOLTAGE DROPOUT CONVERTER(VDC) CHARACTERISTICS
POWER-ON RESET CHARACTERISTICS
AC CHARACTERISTICS
USART CHARACTERISTICS
Figure 7-2 SPI master mode timing (UCPHA = 0, MSB first)
Figure 7-4 SPI slave mode timing (UCPHA = 0, MSB first)
REMOUT PORT CHARACTERISTICS
TYPICAL CHARACTERISTICS
MEMORY
IRAM
Figure 8-3 Lower 128 Byte of IRAM
Figure 8-4 PSW Register
XRAM
Registers
I/O PORTS
Interrupt Controller
External Interrupt
Interrupt Vectors
Effective time of Interrupt Request
Multiple Interrupts
Interrupt Service Procedure
Saving and Restoring General Purpose Registers
Interrupt Registers
Peripheral Units
Basic Interval Timer (BIT)
Watch Dog Timer (WDT)
Figure 11-4 WDT Interrupt and Reset Timing
TIMER/PWM
Figure 11-5 Block Diagram of Timer 0,1 in 8-bit timer/counter mode
Figure 11-6 Interrupt Period of Timer 0, 1
Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode
Figure 11-9 Block Diagram of Timer 0, 1 in 8-bit Capture mode
Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode
Figure 11-12 Block Diagram of Timer 0, 1 in 16-bit Capture Mode
Figure 11-13 Block Diagram of Timer 1 in PWM mode
Figure 11-16 Block Diagram of 16-bit Timer 2 in Output Compare or Event Counter Mode
Figure 11-18 Block Diagram of Timer 2 in Carrier Counting Mode
Figure 11-19 Block Diagram of Timer 3 in Output Compare or Event Counter Mode
Figure 11-20 Block Diagram of Timer 3 in Capture Mode
Figure 11-21 Block Diagram of Timer 3 in Carrier Counting Mode
Figure 11-22 Block Diagram of Timer 3 in PWM Mode
Watch Timer with event capture function (WT)
Figure 11-25 Block Diagram of Watch Timer in IR capture mode
IR Capture Control (IRCC)
Carrier Generator
Figure 11-30 Period of Carrier signal and Remote data pulse
Figure 11-31 REMOUT by CRF & ROB (In case of CEN=1, RDPE=1)
Figure 11-33 REMOUT by RODR
Key Scan
USART0/1
Figure 11-35 The Block Diagram of USART
Figure 11-36 The Block Diagram of Clock Generation
Figure 11-37 Synchronous Mode XCKn Timing
Figure 11-38 frame format
Figure 11-39 Start Bit Sampling
Figure 11-40 The Sampling of Data and Parity Bit
Figure 11-42 SPI Clock Formats when UCPHA=0
Figure 11-43 SPI Clock Formats when UCPHA=1
Figure 11-46 START and STOP Condition
Figure 11-47 STOP or Repeated START Condition
Figure 11-49 Clock Synchronization during Arbitration Procedure
Figure 11-51 Formats and States in the Master Transmitter Mode
Figure 11-52 Formats and States in the Master Receiver Mode
Figure 11-53 Formats and States in the Slave Transmitter Mode
Figure 11-54 Formats and States in the Slave Receiver Mode
POWER MANAGEMENT
STOP mode
Figure 12-3 Wake-up from STOP mode by an interrupt
BOD mode
Register Map
RESET
Noise Canceller for External Reset Pin
Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly)
Figure 13-6 Operation according to Power Level
External RESETB Input
Brown Out Detector
On-chip Debug System
Two-pin external interface
Figure 14-2 10-bit transmission packets
Figure 14-4 Bit transfer on the serial bus
Figure 14-7 Clock synchronization during wait procedure
FLASH Memory Controller
Register Description
Memory map
Serial In-System Program Mode
Security
FLASH Memory operating mode
FUSE Control Register
APPENDIX
MC96FR364B
November, 2018 Rev.1.4
1
ABOV SEMICONDUCTOR Co., Ltd.
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BIT MICROCONTROLLERS
MC
96
FR364B
User
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MC96FR364B
