MC96F6432236 June 22, 2018 Ver. 2.911.13.5 USI1 External Clock (SCK1)External clocking is used in the synchronous mode of operation.External clock input from the SCK1 pin is sampled by a synchronization logic to remove meta-stability. Theoutput from the synchronization logic must be passed through an edge detector before it is used by thetransmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of theexternal SCK1 pin is limited up-to 1MHz.11.13.6 USI1 Synchronous mode operationWhen synchronous or SPI mode is used, the SCK1 pin will be used as either clock input (slave) or clock output(master). Data sampling and transmitter is issued on the different edge of SCK1 clock each other. For example, ifdata input on RXD1 (MISO1 in SPI mode) pin is sampled on the rising edge of SCK1 clock, data output on TXD1(MOSI1 in SPI mode) pin is altered on the falling edge.The CPOL1 bit in USI1CR1 register selects which SCK1 clock edge is used for data sampling and which is usedfor data change. As shown in the figure below, when CPOL1 is zero, the data will be changed at rising SCK1edge and sampled at falling SCK1 edge.Figure 11.80 Synchronous Mode SCK1 Timing (USI1)SCK1TXD1/RXD1CPOL1 = 1TXD1/RXD1SCK1CPOL1 = 0SampleSample
