Xilinx SP605 Hardware User's Manual

Also see for SP605: Hardware Tutorial User guide Hardware setup guide

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Xilinx SP605 Hardware User's Manual Manual pdf 33 page image

SP605 Hardware User Guide www.xilinx.com 33UG526 (v1.9) February 14, 2019Detailed Description10. SFP Module ConnectorThe board contains a small form-factor pluggable (SFP) connector and cage assembly thataccepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FPGA. TheSFP module serial ID interface is connected to the “SFP” IIC bus (see 14. IIC Bus for moreinformation). The control and status signals for the SFP module are connected to jumpersand test points as described in Table 1-12. The SFP module connections are shown inTable 1-13.Table 1-12: SFP Module Control and StatusSFP Control/Status Signal Board ConnectionSFP_TX_FAULTTest Point J15High = FaultLow = Normal OperationSFP_TX_DISABLEJumper J44On = SFP EnabledOff = SFP DisabledSFP_MOD_DETECTTest Point J16High = Module Not PresentLow = Module PresentSFP_RT_SELJumper J22Jumper Pins 1-2 = Full BandwidthJumper Pins 2-3 = Reduced BandwidthSFP_LOSTest Point J14High = Loss of Receiver SignalLow = Normal OperationTable 1-13: SFP Module ConnectionsU1 FPGA Pin Schematic Net Name P2 SFP Module ConnectorPin Number Pin NameD13 SFP_RX_P 13 RDPC13 SFP_RX_N 12 RDNB14 SFP_TX_P 18 TDPA14 SFP_TX_N 19 TDNT17 SFP_LOS 8 LOSY8 SFP_TX_DISABLE_FPGA 3 TX_DISABLEA12 SFPCLK_QO_N (1) U47.6 (2) -B12 SFPCLK_QO_P (1) U47.7 (2) -Notes:1. The 125MHz SFP clock is sourced by clock driver U47.2. Not P2 SFP module pins.