Xilinx ML605 User Manual

Also see for Virtex-6 FPGA: User guide Guide Hardware setup guide User guide User guide

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Xilinx ML605 User Manual Manual pdf 2 page image

ML605 Hardware User Guide www.xilinx.com UG534 (v1.2.1) January 21, 2010Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHERWARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANYWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTYRIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.© 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinxin the United States and other countries. All other trademarks are the property of their respective owners. PCI, PCI Express, PCIe, andPCI-X are trademarks of PCI-SIG.Revision HistoryThe following table shows the revision history for this document.Date Version Revision8/17/09 1.0 Initial Xilinx release.11/17/09 1.1 • Updated Figure 1-1, Figure 1-2, Figure 1-3, Figure 1-11, and Figure 1-14.• Added Figure 1-7, Figure 1-8, Figure 1-10, and Figure 1-13.• Updated Table 1-15 and Table 1-18.• Updated Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout”and Appendix C, “ML605 Master UCF.”• Minor typographical edits.01/15/10 1.2 • Updated Figure 1-2, Figure 1-3, Figure 1-17, Table 1-3, Table 1-8, Table 1-9, Table A-1,and Table A-2. Miscellaneous typographical edits.1/21/10 1.2.1 • Corrected typos in Table 1-31 and Figure 1-28.