Ublox TIM-5H Hardware Integration Manual

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Ublox TIM-5H Hardware Integration Manual Manual pdf 13 page image

TIM-5H - Hardware Integration Manual Design-InGPS.G5-MS5-07015-A-1 u-blox proprietary Page 13your position is our focus2.4 I/O Pins2.4.1 RESET_NAs with ANTARIS 4 versions, TIM-5H comes equipped with a RESET_N pin. Driving the signal low at RESET_Nactivates a hardware reset of the system. Unlike LEA-4x modules, RESET_N is not an I/O with TIM-5H. It is onlyan input and will not reset external circuitry.Use components with open drain output (i.e. with buffer or voltage supervisor ).There is an internal pull up resistor of 3k3 to VCC inside the module that requires that the reset circuitry candeliver enough current (e.g. 1mA).RESET_N is provided with TIM-5H to provide Reset compatibility with ANTARIS 4 versions. Future TIM modelsmay not include this pin and it is therefore not recommended to use it. The preferred option for executing ahardware reset is to send software commands (CFG-RST).Do not drive RESET_N high.2.4.2 EXTINT0EXTINT0 is an external interrupt pin with fixed input voltage thresholds independent of VCC (see the TIM-5HData Sheet [3]). Leave open if unused.2.4.3 AADET_NAADET_N is an input pin and is used to report whether an external circuit has detected a external antenna ornot. Low means antenna has been detected. High means no external antenna has been detected.See chapter 2.9.4 for an implementation example.