Ublox NEO-6 Integration Manual

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Ublox NEO-6 Integration Manual Manual pdf 78 page image

LEA-6 / NEO-6 / MAX-6 - Hardware Integration ManualUBX-14054794 Production Information AppendixPage 78 of 85 Are the high and low level voltages on SDA and SCL correct during I2C transfers? The I2C standard definesthe low level threshold with 0.3 Vcc, the high level threshold with 0.7 Vcc. Modifying the terminationresistance Rp, the serial resistors Rs or lowering the SCL clock rate could help here. Are there spikes or noise on SDA, SCL or even Vdd? They may result from interferences from othercomponents or because the capacitances Cp and/or Cc are too high. The effects can often be reduced byusing shorter interconnections.For more information about DDC implementation refer to the u-blox 6 Receiver Description includingProtocol Specification [4].C.2 SPI InterfaceC.2.1 SPI basicsDevices communicate in master/slave mode where the master device provides the clock signal (SCK) anddetermines the state of the chip select (SCS/SS_N) lines, i.e. it activates the slave it wants to communicate with.The slave device receives the clock and chip select from the master. Multiple slave devices are allowed withindividual slave select (chip select) lines. This means that there is one master, while the number of slaves is onlylimited by the number of chip selects. In addition to reliability and relatively high speed (with respect to theconventional UART), the SPI interface is easy to use and requires no special handling or complex communicationstack implementation in the software.The standard configuration for a slave device (see Figure 68) uses two control and two data lines. These areidentified as follows: SCS — Slave Chip Select (control: output from master, usually active low) SCK — Serial Clock (control: output from master) MOSI — Master Output, Slave Input (data: output from master) MISO — Master Input, Slave Output (data: output from slave)Alternative naming conventions are also widely used. Confirm the pin/signal naming with specificcomponents used.SPI SlaveMISOMOSISCKSCSFigure 68: SPI slaveSPI always follows the basic principle of a shift register. During an SPI transfer, command codes and data valuesare simultaneously transmitted (shifted out serially) and received (shifted in serially). The data is entered into ashift register and then internally available for parallel processing. The length of the shift registers is not fixed, butcan vary from device to device. Normally the shift registers are 8Bit or integral multiples thereof. However, theycan also have an odd number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data.When an SPI transfer occurs, an 8-bit character is shifted out one data pin while a different 8-bit character issimultaneously shifted in a second data pin. Another way to view this transfer is that an 8-bit shift register in themaster and another 8-bit shift register in the slave are connected as a circular 16-bit shift register. When atransfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master andslave are effectively exchanged.The serial clock (SCK) line synchronizes shifting and sampling of the information on the two serial data lines(MOSI and MISO). The chip select (SCS/SS_N) line allows individual selection of a slave SPI device. If an SPI slave