Sony 486DX User Manual

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AR-B1474 User°¶s Guide2-7Name Description-MASTER [Input] The MASTER is the signal from the I/O processor whichgains control as the master and should be held low for amaximum of 15 microseconds or system memory may belost due to the lack of refresh-MEMCS16[Input, Opencollector]The Memory Chip Select 16 indicates that the presentdata transfer is a 1-wait state, 16-bit data memoryoperation-IOCS16[Input, Opencollector]The I/O Chip Select 16 indicates that the present datatransfer is a 1-wait state, 16-bit data I/O operationOSC [Output] The Oscillator is a 14.31818 MHz signalZWS[Input, Opencollector]The Zero Wait State indicates to the microprocessor thatthe present bus cycle can be completed without insertingadditional wait cycleTable 2-6 ISA Bus Signal Description2.4 SERIAL PORTThe ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used to convert parallel data to a serialformat on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order oftransmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,one and half (five-bit format only) or two stop bits. The ACEs are capable of handling divisors of 1 to 65535, andproduce a 16x clock for driving the internal transmitter logic.Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completedMODEM control capability, and a processor interrupt system that may be software tailored to the computing timerequired handle the communications link.The following table is summary of each ACE accessible registerDLAB Port Address RegisterReceiver buffer (read)0 base + 0Transmitter holding register (write)0 base + 1 Interrupt enableX base + 2 Interrupt identification (read only)X base + 3 Line controlX base + 4 MODEM controlX base + 5 Line statusX base + 6 MODEM statusX base + 7 Scratched register1 base + 0 Divisor latch (least significant byte)1 base + 1 Divisor latch (most significant byte)Table 2-7 ACE Accessible Registers(1) Receiver Buffer Register (RBR)Bit 0-7: Received data byte (Read Only)(2) Transmitter Holding Register (THR)Bit 0-7: Transmitter holding data byte (Write Only)