Sony 486DX User Manual

Contents

AR-B1474 User°¶s Guide2-62.3.5 ISA Bus Signal DescriptionName DescriptionBUSCLK [Output] The BUSCLK signal of the I/O channel is asynchronous tothe CPU clock.RSTDRV [Output] This signal goes high during power-up, low line-voltage orhardware resetSA0 - SA19[Input / Output]The System Address lines run from bit 0 to 19. They arelatched onto the falling edge of "BALE"LA17 - LA23[Input/Output]The Unlatched Address line run from bit 17 to 23SD0 - SD15[Input/Output]System Data bit 0 to 15BALE [Output] The Buffered Address Latch Enable is used to latch SA0 -SA19 onto the falling edge. This signal is forced highduring DMA cycles-IOCHCK [Input] The I/O Channel Check is an active low signal whichindicates that a parity error exist on the I/O boardIOCHRDY[Input, Opencollector]This signal lengthens the I/O, or memory read/write cycle,and should be held low with a valid addressIRQ 3-7, 9-12, 14, 15[Input]The Interrupt Request signal indicates I/O service requestattention. They are prioritized in the following sequence :(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)-IOR[Input/Output]The I/O Read signal is an active low signal which instructsthe I/O device to drive its data onto the data bus-IOW [Input/Output] The I/O write signal is an active low signal which instructsthe I/O device to read data from the data bus-SMEMW [Output] The System Memory Read is low while any of the low 1mega bytes of memory are being used-MEMR[Input/Output]The Memory Read signal is low while any memorylocation is being read-SMEMW [Output] The System Memory Write is low while any of the low 1mega bytes of memory is being written-MEMW[Input/Output]The Memory Write signal is low while any memorylocation is being writtenDRQ 0-3, 5-7[Input]DMA Request channels 0 to 3 are for 8-bit data transfers.DMA Request channels 5 to 7 are for 16-bit datatransfers. DMA request should be held high until thecorresponding DMA has been completed. DMA requestpriority is in the following sequence:(Highest) DRQ 0, 1, 2,3, 5, 6, 7 (Lowest)-DACK 0-3, 5-7[Output]The DMA Acknowledges 0 to 3, 5 to 7 are thecorresponding acknowledge signals for DRQ 0 to 3 and 5to 7AEN [output] The DMA Address Enable is high when the DMAcontroller is driving the address bus. It is low when theCPU is driving the address bus-REFRESH[Input/Output]This signal is used to indicate a memory refresh cycle andcan be driven by the microprocessor on the I/O channelTC [Output] Terminal Count provides a pulse when the terminal countfor any DMA channel is reachedSBHE[Input/Output]The System Bus High Enable indicates the high byte SD8- SD15 on the data bus