NEC VT440 Service Manual

Also see for MultiSync VT440: User manual Installation data Specifications User manual

NEC VT440 Service Manual Manual pdf 74 page image

6-1CIRCUIT DESCRIPTIONLC driver block1. Circuit configuration1-1 PWB configuration• MAIN PWBUsed for the phase decode processing of the RGB video signals, the level adjustment, and the genera-tion of various timing signals.• Used for the level shift processing of the panel drive timing signals for the LCES PWB (SVGA) and theLCEX PWB (XGA), and also for the generation of panel auxiliary signals.• The above-mentioned two types of PWBs are connected through the FFC (Flexible Flat Cable) cablesof 40 pins (POSV) and 30 pins (POST).2. Output signal2-1 Signal level• RGB video signal : 10.0Vp-p (2.0V/12.0V)• Panel driving signal : 15.5Vp-p (0.0V/15.5V)• Panel aux. signal : 5.0Vp-p (2.5V/7.5V)2-2 Driver panel• SVGA : Model 0.9 LC panel (P09SG210) by EPSON• XGA : Model 0.9 LC panel (P09XG210) by EPSON3. Outline hardware description3-1 RGB video signalThis signal output is generated from the signal processing circuit G/A, UNI2 (IC3601), on the main board(MAIN PWB). Each 10-bit R,G,B digital video signal (3.3Vp-p) is processed for 6/12 (SVGA/XGA) phasedecode processing by the phase decoding ICs (IC3701, 3702, 3703, 3704, 3705, 3706), and also for thelevel adjustment (10.0Vp-p (2.0V/12.0V)) by the serial D/A (IC3711). Since then, each signal is fed to theLC panel through the LC driver boards (LCES PWB/ LCEX PWB).3-2 Panel driving signalThis signal output is generated from the signal processing circuit G/A, YAMAG (IC3701), on the samemain board (MAIN PWB). The panel drive timing signal (3.3Vp-p) is processed for level shifting to the level(15.5Vp-p) required to drive the shift register in the LC panel by the aid of the level shift ICs (IC5201, 5202,5203/ IC6201, 6202, 6203) located on the LC driver boards (LCES PWB/ LCEX PWB). Since then, theprocessed signal is fed to the LC panel.3-3 Panel auxiliary signalThis signal output is generated from the LC panel signal processing circuit G/A, YAMAG (IC3701), on thesame main board (MAIN PWB). The panel auxiliary signal (3.3Vp-p) is processed for level shifting to thelevel (5.0Vp-p, (2.5V/7.5V)) required to pre-charge the video line in the LC panel by the aid of the levelshift ICs (IC5201, 5202, 5203/ IC6201, 6202, 6203) located on the LC driver boards (LCES PWB/ LCEXPWB). Since then, the processed signal is fed to the LC panel via the diamond buffer of the complextransistor group.