HP 330 Service Information Manual

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Direct Memory AddressingDMA chip architecture is a compatible superset of the HP 98620B DMA Controller which is usedwith HP 9000 series 200 and 300 computers. The chip is a Standard-Cell design implementedin a CMOS process.Refer to Table 3-7 for DMA specifications.Table 3-7. DMA SpecificationsFeatureInput ClockChannelsChannel PriorityChannel ArbitrationBus ArbitrationTransfer TypesMax TransfersBus Bandwidth Use LimitsMin Cycle TimeMax Theoretical Transfer RateTypical Burst Transfer RateInterrupt levelsAddress rangeLAN InterfaceSpecification10 MHz2Programmable, high or low, each channelRound-robinDI0 daisy chain8-bit (byte)16-bit (word)32-bit (long word)4G transfers per armingProgrammable: 100%, 50%, 25%, 12.5%300 ns13.3 Mbytes/sec2.8 Mbytes/sec (word transfers to RAMcontroller boardsProgrammable: 7, 6, 5, 4, 3FFFFFFFF - 00000000Local Area Network (LAN) functions are divided into three areas:• Backplane interface to the DIO-II bus.• Shared melIlory area.• Frontplane interface to the network.Interface with the DIO-II bus includes select code decoding, interrupt control, data bus buffersand latches, and address multiplexers. A 16-bit wide data bus is used.The shared memory area has the memory controller circuits, 16 Kbytes of RAM, 64 nybblesof nonvolatile storage of the node address, and standard DIO control, status, and ID registers.Multiplexing of DIO-II information and the LAN chip set is also part of the controller circuit.102 Functional Description