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Fujitsu 8FX Hardware Manual Manual pdf 1 page image

Fujitsu 8FX Hardware Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. CHAPTER 1 MEMORY ACCESS MODE
  10. Memory Access Mode
  11. CHAPTER 2 CPU
  12. Dedicated Registers
  13. Register Bank Pointer (RP)
  14. Direct Bank Pointer (DP)
  15. Condition Code Register (CCR)
  16. General-purpose Register
  17. Placement of 16-bit Data in Memory
  18. CHAPTER 3 CLOCK CONTROLLER
  19. Overview
  20. clock modes
  21. Oscillation Stabilization Wait Time
  22. Registers
  23. System Clock Control Register (SYCC)
  24. PLL Control Register (PLLC)
  25. Oscillation Stabilization Wait Time Setting Register (WATR)
  26. Standby Control Register (STBC)
  27. System Clock Control Register 2 (SYCC2)
  28. Standby Control Register 2 (STBC2)
  29. Clock Modes
  30. Operations in Low Power Consumption Mode (Standby Mode)
  31. Notes on Using Standby Mode
  32. Sleep Mode
  33. Stop Mode
  34. Time-base Timer Mode
  35. Watch Mode
  36. Clock Oscillator Circuit
  37. Overview of Prescaler
  38. Configuration of Prescaler
  39. Operation of Prescaler
  40. Notes on Using Prescaler
  41. CHAPTER 4 RESET
  42. Reset Operation
  43. Register
  44. Reset Source Register (RSRR)
  45. Notes on Using Reset
  46. CHAPTER 5 INTERRUPTS
  47. Interrupts
  48. Interrupt Level Setting Registers (ILR0 to ILR5)
  49. Interrupt Processing
  50. Nested Interrupts
  51. Interrupt Processing Time
  52. Stack Operation During Interrupt Processing
  53. Interrupt Processing Stack Area
  54. CHAPTER 6 I/O PORT
  56. Configuration and Operations
  57. CHAPTER 7 TIME-BASE TIMER
  59. Configuration
  60. Interrupt
  61. Operations and Setting Procedure Example
  63. Time-base Timer Control Register (TBTC)
  64. Notes on Using Time-base Timer
  68. CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER
  69. Watchdog Timer Control Register (WDTC)
  70. Notes on Using Watchdog Timer
  71. CHAPTER 9 WATCH PRESCALER
  77. Watch Prescaler Control Register (WPCR)
  78. Notes on Using Watch Prescaler
  79. CHAPTER 10 WILD REGISTER FUNCTION
  82. Operations
  84. Wild Register Data Setting Registers (WRDR0 to WRDR2)
  85. Wild Register Address Setting Registers (WRAR0 to WRAR2)
  86. Wild Register Address Compare Enable Register (WREN)
  87. Wild Register Data Test Setting Register (WROR)
  88. Typical Hardware Connection Example
  89. CHAPTER 11 8/16-BIT COMPOSITE TIMER
  92. Channel
  93. Pins
  95. Operation of Interval Timer Function (One-shot Mode)
  96. Operation of Interval Timer Function (Continuous Mode)
  97. Operation of Interval Timer Function (Free-run Mode)
  98. Operation of PWM Timer Function (Fixed-cycle Mode)
  99. Operation of PWM Timer Function (Variable-cycle Mode)
  100. Operation of PWC Timer Function
  101. Operation of Input Capture Function
  102. Operation of Noise Filter
  104. bit Composite Timer Status Control Register 0 (Tn0CR0/Tn1CR0)
  105. bit Composite Timer Status Control Register 1 (Tn0CR1/Tn1CR1)
  106. bit Composite Timer Timer Mode Control Register (TMCRn)
  107. bit Composite Timer Data Register (Tn0DR/Tn1DR)
  108. Notes on Using 8/16-bit Composite Timer
  109. CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT
  112. Channels
  116. External Interrupt Control Register (EIC)
  117. Notes on Using External Interrupt Circuit
  118. CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT
  122. Operation
  124. Interrupt Pin Selection Circuit Control Register (WICR)
  125. Notes on Using Interrupt Pin Selection Circuit
  126. CHAPTER 14 LIN-UART
  129. reload counter
  132. Timing of Receive Interrupt Generation and Flag Set
  133. Timing of Transmit Interrupt Generation and Flag Set
  134. LIN-UART Baud Rate
  135. Baud Rate Setting
  136. Reload Counter
  137. Operations of LIN-UART and LIN-UART Setting Procedure Example
  138. Operations in Asynchronous Mode (Operating Mode 0, 1)
  139. Operations in Synchronous Mode (Operating Mode 2)
  140. Operations of LIN function (Operating Mode 3)
  141. Serial Pin Direct Access
  142. Bidirectional Communication Function (Normal Mode)
  143. Master/Slave Mode Communication Function (Multiprocessor Mode)
  144. LIN Communication Function
  145. Examples of LIN-UART LIN Communication Flow Chart (Operating Mode 3)
  147. LIN-UART Serial Control Register (SCR)
  148. LIN-UART Serial Mode Register (SMR)
  149. LIN-UART Serial Status Register (SSR)
  150. LIN-UART Receive Data Register/LIN-UART Transmit Data Register (RDR/TDR)
  151. LIN-UART Extended Status Control Register (ESCR)
  152. LIN-UART Extended Communication Control Register (ECCR)
  153. LIN-UART Baud Rate Generator Registers 1, 0 (BGR1, BGR0)
  154. Notes on Using LIN-UART
  155. CHAPTER 15 8/10-BIT A/D CONVERTER
  161. bit A/D Converter Control Register 1 (ADC1)
  162. bit A/D Converter Control Register 2 (ADC2)
  163. bit A/D Converter Data Register (Upper/Lower) (ADDH/ADDL)
  164. Notes on Using 8/10-bit A/D Converter
  165. CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT
  171. LVD Reset Voltage Selection ID Register (LVDR)
  172. CHAPTER 17 CLOCK SUPERVISOR COUNTER
  177. Clock Monitoring Data Register (CMDR)
  178. Clock Monitoring Control Register (CMCR)
  179. Notes on Using Clock Supervisor Counter
  180. CHAPTER 18 8/16-BIT PPG
  187. bit PPG Independent Mode
  188. bit Prescaler + 8-bit PPG Mode
  189. bit PPG Mode
  191. bit PPG timer n1 Control Register (PCn1)
  192. bit PPG timer n0 Control Register (PCn0)
  193. bit PPG timer n1/n0 Cycle Setup Buffer Register (PPSn1/PPSn0)
  194. bit PPG timer n1/n0 Duty Setup Buffer Register (PDSn1/PDSn0)
  195. bit PPG Start Register (PPGS)
  196. bit PPG Output Reverse Register (REVC)
  197. Notes on Using 8/16-bit PPG
  198. CHAPTER 19 16-BIT PPG TIMER
  206. bit PPG Downcounter Register (Upper/Lower) ch. n (PDCRHn/PDCRLn)
  207. bit PPG Cycle Setting Buffer Register (Upper/ Lower) ch. n PCSRHn/PCSRLn)
  208. bit PPG Duty Setting Buffer Register (Upper/Lower) ch. n (PDUTHn/PDUTLn)
  209. bit PPG Status Control Register (Upper) ch. n (PCNTHn)
  210. bit PPG Status Control Register (Lower) ch. n (PCNTLn)
  211. Notes on Using 16-bit PPG Timer
  212. CHAPTER 20 16-BIT RELOAD TIMER
  219. Internal Clock Mode
  220. Event Count Mode
  222. bit Reload Timer Control Status Register (Upper) ch. n (TMCSRHn)
  223. bit Reload Timer Control Status Register (Lower) ch. n (TMCSRLn)
  224. bit Reload Timer Timer Register (Upper/Lower) ch. n (TMRHn/TMRLn)
  225. bit Reload Timer Reload Register (Upper/Lower) ch. n (TMRLRHn/TMRLRLn)
  226. Notes on Using 16-bit Reload Timer
  227. CHAPTER 21 MULTI-PULSE GENERATOR
  229. Block Diagram
  233. Operation of Position Detection
  234. Operation of Data Write Control Unit
  235. Operation of 16-bit MPG Output Data Buffer Register (Upper/Lower OPDBRHx/OPDBRLx)
  236. Operation of Data Transfer of 16-bit MPG Output Data Register (Upper/Lower)
  237. At OPDBRH0 and OPDBRL0 Write
  238. At 16-bit Reload Timer Underflow
  239. At Position Detection
  240. At Position Detection and Timer Underflow
  241. At Position Detection or Timer Underflow
  242. At One-shot Position Detection
  243. When One-shot Position Detection and Reload Timer Underflow
  244. When One-shot Position Detection or Reload Timer Underflow
  245. Operation of DTTI Input Control
  246. Operation of Noise Cancellation Function
  247. Operation of 16-bit Timer
  249. bit MPG Output Control Register (Upper) (OPCUR)
  250. bit MPG Output Control Register (Lower) (OPCLR)
  251. bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR)
  252. bit MPG Output Data Register (Upper) (OPDUR)
  253. bit MPG Output Data Register (Lower) (OPDLR)
  254. bit MPG Output Data Buffer Register (Upper/Lower) (OPDBRHx/OPDBRLx)
  255. bit MPG Output Data Buffer Register (Upper) (OPDBRHx)
  256. bit MPG Output Data Buffer Register (Lower) (OPDBRLx)
  257. bit MPG Input Control Register (Upper/Lower) (IPCUR/IPCLR)
  258. bit MPG Input Control Register (Upper) (IPCUR)
  259. bit MPG Input Control Register (Lower) (IPCLR)
  260. bit MPG Compare Clear Register (Upper/Lower) (CPCUR/CPCLR)
  261. bit MPG Timer Buffer Register (Upper/Lower) (TMBUR/TMBLR)
  262. bit MPG Timer Control Status Register (TCSR)
  263. bit MPG Noise Cancellation Control Register (NCCR)
  264. Notes on Using Multi-pulse Generator
  265. Sample Program for Multi-pulse Generator
  266. CHAPTER 22 UART/SIO
  273. Operations in Operation Mode 0
  274. Operations in Operation Mode 1
  276. UART/SIO Serial Mode Control Register 1 ch. n (SMC1n)
  277. UART/SIO Serial Mode Control Register 2 ch. n (SMC2n)
  278. UART/SIO Serial Status and Data Register ch. n (SSRn)
  279. UART/SIO Serial Input Data Register ch. n (RDRn)
  280. UART/SIO Serial Output Data Register ch. n (TDRn)
  281. CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR
  288. CHAPTER 24 I 2 C BUS INTERFACE
  293. Function to Wake up the MCU from Standby Mode
  295. CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
  296. Basic Configuration of Serial Programming Connection
  297. Example of Serial Programming Connection
  298. CHAPTER 26 DUAL OPERATION FLASH MEMORY
  300. Sector/Bank Configuration
  301. Invoking Flash Memory Automatic Algorithm
  302. Checking Automatic Algorithm Execution Status
  303. Data Polling Flag (DQ7)
  304. Toggle Bit Flag (DQ6)
  305. Execution Timeout Flag (DQ5)
  306. Sector Erase Timer Flag (DQ3)
  307. Toggle Bit2 Flag (DQ2)
  308. Programming/Erasing Flash Memory
  309. Placing Flash Memory in Read/Reset State
  310. Programming Data to Flash Memory
  311. Erasing All Data from Flash Memory (Chip Erase)
  312. Erasing Specific Data from Flash Memory (Sector Erase)
  313. Suspending Sector Erase from Flash Memory
  314. Resuming Sector Erase of Flash Memory
  315. Unlock Bypass Program
  317. Flash Security
  319. Flash Memory Status Register 2 (FSR2)
  320. Flash Memory Status Register (FSR)
  321. Flash Memory Sector Write Control Register 0 (SWRE0)
  322. Flash Memory Status Register 3 (FSR3)
  323. Flash Memory Status Register 4 (FSR4)
  324. Notes on Using Dual Operation Flash Memory
  325. CHAPTER 27 NON-VOLATILE REGISTER (NVR) INTERFACE
  329. Main CR Clock Trimming Register (Upper) (CRTH)
  330. Main CR Clock Trimming Register (Lower) (CRTL)
  331. Main CR Clock Temperature Dependent Adjustment Register (CRTDA)
  332. Watchdog Timer Selection ID Register (Upper/Lower) (WDTH/WDTL)
  333. Notes on Main CR Clock Trimming
  334. Notes on Using NVR Interface
  335. CHAPTER 28 COMPARATOR
  342. Comparator Control Register (CMR0C)
  343. CHAPTER 29 SYSTEM CONFIGURATION CONTROLLER
  346. System Configuration Register (SYSC)
  347. Notes on Using Controller
  348. APPENDIX
  349. appendix a instruction overview
  350. A.1 Addressing
  351. A.2 Special Instruction
  352. APPENDIX A Instruction Overview
Fujitsu 8FX Hardware Manual Manual pdf 1 page image
FUJITSU SEMICONDUCTORCONTROLLER MANUAL8-BIT MICROCONTROLLERNew 8FXMB95630H SeriesHARDWARE MANUALMN702-00009-2v0-E
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