Epson S1D13706 Technical Manual

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Epson Research and Development Page 9Vancouver Design CenterInterfacing to 8-bit Processors S1D13706Issue Date: 01/02/23 X31B-G-015-023 S1D13706 Host Bus InterfaceThe S1D13706 directly supports multiple processors. The S1D13706 implements a 16-bitGeneric #2 Host Bus Interface which can be adapted for use with an 8-bit processor.The Generic #2 Host Bus Interface is selected by the S1D13706 on the rising edge ofRESET#. After RESET# is released, the bus interface signals assume their selected config-uration. For details on the S1D13706 configuration, see Section 4.2, “S1D13706 HardwareConfiguration” on page 12.3.1 Host Bus Interface Pin MappingThe following table shows the functions of each Host Bus Interface signal.Table 3-1: Host Bus Interface Pin MappingS1D13706Pin Names Generic #2 CommentsAB[16:0] A[16:0] —DB[15:0] D[15:0] —WE1# Byte High Enable (BHE#) External decode requiredCS# Chip Select External decode requiredM/R# Memory/Register Select External decode requiredCLKI BUSCLK —BS# connect to HIO VDD —RD/WR# connect to HIO V DD —RD# RD# —WE0# WE# —WAIT# WAIT# —RESET# Inverted RESET —