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Epson S1D13706 Technical Manual Manual pdf 614 page image

Epson S1D13706 Technical Manual

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Contents
  1. Riesstrasse
  2. hardware functional specification
  3. Table of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Introduction
  9. Features
  10. Display Modes
  11. Typical System Implementation Diagrams
  12. figure 3-3: typical system diagram (hitachi sh-4 bus)
  13. figure 3-5: typical system diagram (mc68k # 1, motorola 16-bit)
  14. figure 3-7: typical system diagram (motorola redcap2 bus)
  15. Pinout Diagram - TQFP15 - 100pin
  16. Pinout Diagram - CFLGA - 104pin
  17. Pinout Diagram - Die Form
  18. Pin Descriptions
  19. LCD Interface
  20. Clock Input
  21. Summary of Configuration Options
  22. Host Bus Interface Pin Mapping
  23. LCD Interface Pin Mapping
  24. D.C. Characteristics
  25. A.C. Characteristics
  26. Internal Clocks
  27. CPU Interface Timing
  28. Generic #2 Interface Timing (e.g. ISA)
  29. Hitachi SH-4 Interface Timing
  30. Hitachi SH-3 Interface Timing
  31. Motorola MC68K #1 Interface Timing (e.g. MC68000)
  32. Motorola MC68K #2 Interface Timing (e.g. MC68030)
  33. Motorola REDCAP2 Interface Timing
  34. LCD Power Sequencing
  35. Passive/TFT Power-Off Sequence
  36. Display Interface
  37. Generic STN Panel Timing
  38. Issue Date: 01/11/13 Page
  39. Single Monochrome 4-Bit Panel Timing
  40. Single Monochrome 8-Bit Panel Timing
  41. Single Color 4-Bit Panel Timing
  42. Single Color 8-Bit Panel Timing (Format 1)
  43. Single Color 8-Bit Panel Timing (Format 2)
  44. Single Color 16-Bit Panel Timing
  45. Generic TFT Panel Timing
  46. Bit TFT Panel Timing
  47. x160 Sharp 'Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx)
  48. x240 sharp 'direct' hr-tft panel timing (e.g. lq039q2ds)
  49. x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
  50. x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
  51. Clocks
  52. PCLK
  53. PWMCLK
  54. Clock Selection
  55. Clocks versus Functions
  56. Registers
  57. Register Descriptions
  58. Clock Configuration Registers
  59. Look-Up Table Registers
  60. Panel Configuration Registers
  61. Display Mode Registers
  62. Miscellaneous Registers
  63. General IO Pins Registers
  64. Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
  65. Frame Rate Calculation
  66. Display Data Formats
  67. Look-Up Table Architecture
  68. Color Modes
  69. Concept
  70. Register Programming
  73. Picture-in-Picture Plus (PIP+)
  74. with swivelview enabled
  75. Big-Endian Bus Interface 14.1 Byte Swapping Bus Data
  76. Bpp Color Depth
  78. Power Save Mode
  79. Mechanical Data
  80. References
  81. Sales and Technical Support
  82. programming notes and examples
  83. Table of Contents
  84. Table Of Contents
  85. Table Of Contents
  86. memory models
  87. memory organization for two bit-per-pixel (4 colors/gray shades)
  88. memory organization for 8 bpp (256 colors/64 gray shades)
  89. look-up table (lut)
  90. look-up table read registers
  91. look-up table organization
  92. gray shade modes
  93. color modes
  94. power save mode enable
  95. enabling power save mode
  96. enabling the lcd panel
  97. picture-in-picture plus
  98. picture-in-picture-plus examples
  99. identifying the s1d
  100. hardware abstraction layer (hal)
  101. general hal support
  102. advance hal functions
  103. surface support
  104. register access
  105. memory access
  106. color manipulation
  107. virtual display
  108. register/display memory
  109. porting libse to a new target platform
  110. building the libse library for sh3 target example
  111. sample code
  112. cfg configuration program
  113. Table of Contents
  114. Table Of Contents
  115. cfg configuration tabs
  116. preferences tab
  117. clocks tab
  118. panel tab
  119. panel power tab
  120. registers tab
  121. cfg menus
  122. save as
  123. configure multiple
  124. enable tooltips
  125. installation guide
  126. Table of Contents
  127. Table Of Contents
  128. list of figures
  129. installation and configuration
  130. configuration jumpers
  131. cpu interface pin mapping
  132. cpu bus connector pin mapping
  133. direct host bus interface support
  134. manual/software adjustable lcd panel negative power supply (vlcd)
  135. software adjustable lcd backlight intensity support using pwm
  136. clock synthesizer and clock options
  137. document sources
  138. parts list
  139. board layout
  140. technical support
  141. hardware description
  142. power consumption
  143. Table of Contents
  144. Table Of Contents
  145. interfacing to the mpc
  146. memory controller module
  147. user-programmable machine (upm)
  148. mpc821 to s1d13706 interface
  149. mpc821ads evaluation board hardware connections
  150. mpc821 chip select configuration
  151. Table of Contents
  152. Table Of Contents
  153. connecting to the sharp lq039q2ds01 hr-tft
  154. s1d13706 to lq039q2ds01 pin mapping
  155. connecting to the sharp lq031b1ddxx hr-tft
  156. s1d13706 to lq031b1ddxx pin mapping
  157. sharp hr-tft panel
  158. Table of Contents
  159. Table Of Contents
  160. vddh and vdd - horizontal and vertical analog voltages
  161. veey - lcd panel drive voltage for vertical power supplies - brightness reference
  162. vcc - horizontal logic power supply
  163. swing power supply for the vertical drive (v0y) and logic (vccy / v5y) voltages
  164. level shift and clamp circuit for vertical logic control signals
  165. s1d13706 to d-tfd panel pin mapping
  166. lcd pin mapping for horizontal connector (lf37sqt and lf26sct)
  167. lcd pin mapping for y connector (lf37sqt)
  168. lcd pin mapping for y connector (lf26sct)
  169. power-on/off sequence
  170. gcp data signal
  171. programming gcp data
Epson S1D13706 Technical Manual Manual pdf 614 page image
Page 4 Epson Research and DevelopmentVancouver Design CenterS1D13706 Interfacing to 8-bit ProcessorsX31B-G-015-02 Issue Date: 01/02/23THIS PAGE LEFT BLANK
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