OneStart

Menu

Davicom DM9000 Manual

Page 1 preview
Page 2 preview
Page 3 preview
Page 4 preview
Page 5 preview
Page 6 preview
Page 7 preview
Page 8 preview
Page 9 preview
Page 10 preview
Page 11 preview
Page 12 preview
Page 13 preview
Page 14 preview
Page 15 preview
Page 16 preview
Page 17 preview
Page 18 preview
Page 19 preview
Page 20 preview
Page 21 preview
Page 22 preview
Page 23 preview
Page 24 preview
Page 25 preview
Page 26 preview
Page 27 preview
Page 28 preview
Page 29 preview
Page 30 preview
Page 31 preview
Page 32 preview
Page 33 preview
Page 34 preview
Page 35 preview
Page 36 preview
Page 37 preview
Page 38 preview
Page 39 preview
Page 40 preview
Page 41 preview
Page 42 preview
Page 43 preview
Page 44 preview
Page 45 preview
Page 46 preview
Page 47 preview
Page 48 preview
Page 49 preview
Page 50 preview
Page 51 preview
Page 52 preview
Page 53 preview
Page 54 preview
Page 55 preview
Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Features
  4. Pin Configuration
  5. Pin Configuration II: with 32-Bit Data Bus
  6. Pin Description
  7. Processor Interface
  8. Clock Interface
  9. Power Pins
  10. Vendor Control and Status Register Set
  11. Network Control Register (00H)
  12. TX Status Register I (03H)
  13. RX Status Register (06H)
  14. Flow Control Threshold Register (09H)
  15. ROM & PHY Address Register (0CH)
  16. Multicast Address Register (16H~1DH)
  17. Vendor ID Register (28H~29H)
  18. Memory Data Write Command with Address Increment Register (F8H)
  19. EEPROM Format
  20. MII Register Description
  21. Basic Mode Control Register (BMCR) – 00
  22. Basic Mode Status Register (BMSR) – 01
  23. PHY ID Identifier Register #1 (PHYID1) – 02
  24. Auto-negotiation Advertisement Register ANAR) – 04
  25. Auto-negotiation Link Partner Ability Register ANLPAR) – 05
  26. DAVICOM Specified Configuration Register DSCR) – 16
  27. DAVICOM Specified Configuration and Status Register (DSCSR) – 17
  28. Functional Description
  29. Base-TX Operation
  30. B5B Code Group
  31. Base-TX Receiver
  32. Code Group Alignment
  33. Power Reduced Mode
  34. DC and AC Electrical Characteristics
  35. DC Electrical Characteristics
  36. AC Electrical Characteristics & Timing Waveforms
  37. Processor Register Write Timing
  38. External MII Interface Transmit Timing
  39. MII Management Interface Timing
  40. Application Notes
  41. Magnetics Selection Guide
  42. Package Information
  43. Appendix
  44. Order Information
Davicom DM9000 Manual Manual pdf 1 page image
DM9000ISA to Ethernet MAC Controller with Integrated 10/100 PHYFinal 1Version: DM9000-DS-F02June 26, 20021. General DescriptionThe DM9000 is a fully integrated and cost-effectivesingle chip Fast Ethernet MAC controller with ageneral processor interface, a 10/100M PHY and 4KDword SRAM. It is designed with low power and highperformance process that support 3.3V with 5Vtolerance.The DM9000 also provides a MII interface to connectHPNA device or other transceivers that support MIIinterface. The DM9000 supports 8-bit, 16-bit and 32-bit uP interfaces to internal memory accesses fordifferent processors. The PHY of the DM9000 caninterface to the UTP3, 4, 5 in 10Base-T and UTP5 in100Base-TX. It is fully compliant with the IEEE 802.3u Spec.Its auto-negotiation function will automatically configure theDM9000 to take the maximum advantage of its abilities. TheDM9000 also supports IEEE 802.3x full- duplex flow control.This programming of the DM9000 is very simple, so usercan port the software drivers to any system easily.2. Block DiagramEEPROMInterfaceExternal MIIInterfaceLEDTX+/-RX+/-MII ManagementControl& MII RegisterAutonegotiationMemoryManagementRX MachineTX MachineMACMII100 Base-TXPCS100 Base-TXtransceiver10 Base-TTx/RxPHYceiverControl &StatusRegistersInternalSRAMProcessorInterface
/ 55
Related manuals for Davicom DM9000
Davicom DM9000A Application Notes first page preview
Davicom DM9000A Application Notes
This manual is suitable for:
DM9000
Product
Menu
Learn More
Menu
Legal
Menu
Copyright © 2024 OneStart. All Rights Reserved