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Davicom DM9000 Manual
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DM9000ISA to Ethernet MAC Controller with Integrated 10/100 PHY52 FinalVersion: DM9000-DS-F02June 26, 200213. APPENDIX:1. Data Sheet Changed Errata ListItems Data & Ver. Page Content1 05/02/2001 P01 DM9000 Data Sheet Start2 06/14/2001 P01 Page 1 Modify Block Diagram3 06/22/2001 P01 Page 14 Check TableA-1-A &A-1-B4 12/05/2001 P02 Page 7 Check TableA-2-A &A-2-B5 12/05/2001 P02 Page 11 Check TableA-3-A &A-2-B6 12/05/2001 P02 Page 38 Check TableA-4-A &A-4-BBefore Modification4 BKPM 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when a packet’s DA match and RX SRAM over BPHW3 BKPA 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when any packet coming and RX SRAM over BPHWTable A-1-AAfter Modification4 BKPA 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when any packet coming and RX SRAM over BPHW3 BKPM 0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when a packet’s DA match and RX SRAM over BPHWTable A-1-BBefore Modification16,17,18,19TEST1~TEST4 I Operation ModeTest1,2,3,4=(1,1,0,0) : the processor interface is ISA compatibleTest1,2,3,4=(1,1,0,1) : the processor interface is for general processorTable A-2-AAfter Modification16,17,18,19TEST1~TEST4 I Operation ModeTest1,2,3,4=(1,1,0,0) in normal applicationTable A-2-BBefore ModificationBit Name Default Description2:1 LBK 00,RW Loopback modeBit 2 10 0 normal0 1 MAC internal loopback1 0 internal PHY digital loopback1 1 internal PHY analog loopbackTable A-3-A |
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