Chapter 4 135Post CodesThese tables describe the POST codes and descriptions during the POST.Code Beeps POST Routine Description02h Verify Real Mode03h Disable Non-Maskable Interrupt (NMI)04h Get CPU type06h Initialize system hardware08h Initialize chipset with initial POST values09h Set IN POST flag0Ah Initialize CPU registers0Bh Enable CPU cache0Ch Initialize caches to initial POST values0Eh Initialize I/O component0Fh Initialize the local bus IDE10h Initialize Power Management11h Load alternate registers with initial POST values12h Restore CPU control word during warm boot13h Initialize PCI Bus Mastering devices14h Initialize keyboard controller16h 1-2-2-3 BIOS ROM checksum17h Initialize cache before memory autosize18h 8254 timer initialization1Ah 8237 DMA controller initialization1Ch Reset Programmable Interrupt Controller20h 1-3-1-1 Test DRAM refresh22h 1-3-1-3 Test 8742 Keyboard Controller24h Set ES segment register to 4 GB26h Enable A20 line28h Autosize DRAM29h Initialize POST Memory Manager2Ah Clear 512 KB base RAM2Ch 1-3-4-1 RAM failure on address line xxxx*2Eh 1-3-4-3 RAM failure on data bits xxxx* of low byte of memory bus2Fh Enable cache before system BIOS shadow30h 1-4-1-1 RAM failure on data bits xxxx* of high byte of memory bus32h Test CPU bus-clock frequency33h Initialize Phoenix Dispatch Manager36h Warm start shut down38h Shadow system BIOS ROM3Ah Autosize cache3Ch Advanced configuration of chipset registers3Dh Load alternate registers with CMOS values42h Initialize interrupt vectors
