ADLINK Technology cPCIS-3100 Series User Manual

ADLINK Technology cPCIS-3100 Series User Manual Manual pdf 31 page image

Backplane Options • 21u P4 pin assignments of system slot are all reserved for rear I/Ou P5 pin assignments of system slot are all reserved for rear I/O orconnect to the secondary IDE connector according to the followingdefinition.Pin Z A B C D E F22 GND N/C N/C N/C N/C N/C GND21 GND N/C N/C SDD8 SDD7 SPWRGD GND20 GND N/C N/C SDD9 N/C SDD6 GND19 GND N/C N/C SDD11 SDD10 SDD5 GND18 GND N/C N/C SDD12 N/C SDD4 GND17 GND N/C N/C N/C N/C N/C GND16 GND N/C N/C N/C N/C SDD3 GND15 GND N/C N/C N/C N/C N/C GND14 GND N/C N/C SDD13 N/C SDD2 GND13 GND N/C N/C N/C SDD14 SDD1 GND12 GND N/C N/C SDD15 N/C SDD0 GND11 GND N/C N/C N/C DDRQ1 DIOW1# GND10 GND N/C N/C DIOR1# PDIAG SIORDY GND9 GND N/C N/C N/C N/C DDACK1# GND8 GND N/C N/C SDA1 N/C SIRQ GND7 GND N/C N/C N/C SDA2 SDA0 GND6 GND N/C N/C SCS3# N/C SCS1# GND5 GND N/C N/C N/C N/C N/C GND4 GND N/C N/C N/C N/C N/C GND3 GND N/C N/C N/C N/C N/C GND2 GND N/C N/C N/C N/C N/C GND1 GND N/C N/C N/C N/C N/C GNDNote: 1. The N/C pins are no connection to any other pins.2. The signal pins are reserved for matching with cPCI-6200A CPUboards. These signals are connected to the secondary IDEconnector. All these signals are reserved for users’ own rear I/Oapplication, if users do not use the secondary IDE port.4.1.4 I/O Slot Pin assignmentsu P1 pin assignments are compliant to PCIMG 2.0 R3.0, 32-bitCompactPCI standardNote: 1. The HEATHY# signals is bypassed to Ground by a 0.01uFcapacitor.2. The REQ64# and ACK64# signals are with 2.7KO pull high.3. The graphical address (GA) of the peripheral slot is assigned bythe backplane. They are identical with their respective physical slotnumber.u P2, P3, P5 pin assignments are all none-connected and reserved forrear I/O application.u P4 pin assignments are compliant to PICMG 2.5 H.110 standard