Epson S1C17001 manuals
S1C17001
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Overview
- Block Diagram
- Pins
- Pin Descriptions
- S1C17 Core Features
- CPU Registers
- Command Set
- Vector Table
- Processor Information
- Memory Map and Bus Control
- Bus Cycle
- Internal ROM Area
- Internal RAM Area
- Internal Peripheral Circuit Area
- I/O Map
- Core I/O Reserved Area
- Power Supply Voltage
- Initial Reset
- P0 Port Key-Entry Reset
- Initial Reset Sequence
- Initial Settings at Initial Resetting
- ITC Configuration
- Maskable Interrupt Control
- Interrupt Permission/Prohibition
- Processing for Multiple Interrupts
- Interrupt Trigger Modes
- S1C17 Core Interrupt Processing
- Software Interrupts
- HALT and SLEEP Mode Cancellation by Interrupt Factors
- Control Register Details
- x4300: Interrupt Flag Register (ITC_IFLG)
- x4302: Interrupt Enable Register (ITC_EN)
- x4304: ITC Control Register (ITC_CTL)
- x4306: External Interrupt Level Setup Register 0 (ITC_ELV0)
- x4308: External Interrupt Level Setup Register 1 (ITC_ELV1)
- x430a: External Interrupt Level Setup Register 2 (ITC_ELV2)
- x430c: External Interrupt Level Setup Register 3 (ITC_ELV3)
- x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0)
- x4310: Internal Interrupt Level Setup Register 1 (ITC_ILV1)
- x4312: Internal Interrupt Level Setup Register 2 (ITC_ILV2)
- x4314: Internal Interrupt Level Setup Register 3 (ITC_ILV3)
- Precautions
- Oscillator Circuit (OSC)
- OSC3 Oscillator Circuit
- OSC1 Oscillator Circuit
- System Clock Switching
- bit OSC1 Timer Clock Control
- Clock External Output (FOUT3, FOUT1)
- RESET and NMI Input Noise Filters
- x5060: Clock Source Select Register (OSC_SRC)
- x5061: Oscillation Control Register (OSC_CTL)
- x5062: Noise Filter Enable Register (OSC_NFEN)
- x5064: FOUT Control Register (OSC_FOUT)
- x5065: T8OSC1 Clock Control Register (OSC_T8OSC1)
- Clock Generator (CLG)
- CPU Core Clock (CCLK) Control
- Peripheral Module Clock (PCLK) Control
- x5080: PCLK Control Register (CLG_PCLK)
- x5081: CCLK Control Register (CLG_CCLK)
- Prescaler (PSC)
- Input/Output Port (P)
- Data Input/Output
- Pull-up Control
- Input Interface Level
- P0 Port Chattering Filter Function
- Port Input Interrupt
- x5200/0x5210/0x5220/0x5230: Px Port Input Data Registers (Px_IN)
- x5201/0x5211/0x5221/0x5231: Px Port Output Data Registers (Px_OUT)
- x5202/0x5212/0x5222/0x5232: Px Port I/O Direction Control Registers (Px_IO)
- x5203/0x5213/0x5223/0x5233: Px Port Pull-up Control Registers (Px_PU)
- x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK)
- x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE)
- x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG)
- x5208: P0 Port Chattering Filter Control Register (P0_CHAT)
- x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST)
- x52a0: P0 Port Function Select Register (P0_PMUX)
- x52a1: P1 Port Function Select Register (P1_PMUX)
- x52a2: P2 Port Function Select Register (P2_PMUX)
- x52a3: P3 Port Function Select Register (P3_PMUX)
- bit Timer (T16)
- bit Timer Operating Modes
- External Clock Mode
- Pulse Width Measurement Mode
- Count Mode
- bit Timer Reload Register and Underflow Cycle
- bit Timer Reset
- bit Timer RUN/STOP Control
- bit Timer Output Signal
- bit Timer Interrupts
- x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx)
- x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx)
- x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx)
- x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx)
- bit Timer (T8F)
- bit Timer Count Mode
- Count Clock
- Fine Mode
- x4200: 8-bit Timer Input Clock Select Register (T8F_CLK)
- x4202: 8-bit Timer Reload Data Register (T8F_TR)
- x4204: 8-bit Timer Counter Data Register (T8F_TC)
- x4206: 8-bit Timer Control Register (T8F_CTL)
- PWM & Capture Timer (T16E)
- PWM & Capture Timer Operating Modes
- Setting and Resetting Counter Value
- Compare Data Settings
- PWM & Capture Timer RUN/STOP Control
- Clock Output Control
- PWM & Capture Timer Interrupts
- x5300: PWM Timer Compare Data A Register (T16E_CA)
- x5302: PWM Timer Compare Data B Register (T16E_CB)
- x5304: PWM Timer Counter Data Register (T16E_TC)
- x5306: PWM Timer Control Register (T16E_CTL)
- x5308: PWM Timer Input Clock Select Register (T16E_CLK)
- x530a: PWM Timer Interrupt Mask Register (T16E_IMSK)
- x530c: PWM Timer Interrupt Flag Register (T16E_IFLG)
- bit OSC1 Timer (T8OSC1)
- bit OSC1 Timer Count Mode
- Resetting 8-bit OSC1 Timer
- bit OSC1 Timer RUN/STOP Control
- bit OSC1 Timer Interrupts
- x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL)
- x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT)
- x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP)
- x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK)
- x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG)
- Clock Timer (CT)
- Operation Clock
- Clock Timer Resetting
- Clock Timer RUN/STOP Control
- Clock Timer Interrupts
- x5000: Clock Timer Control Register (CT_CTL)
- x5001: Clock Timer Counter Register (CT_CNT)
- x5002: Clock Timer Interrupt Mask Register (CT_IMSK)
- x5003: Clock Timer Interrupt Flag Register (CT_IFLG)
- Stopwatch Timer (SWT)
- BCD Counters
- Stopwatch Timer Resetting
- Stopwatch Timer RUN/STOP Control
- Stopwatch Timer Interrupts
- x5020: Stopwatch Timer Control Register (SWT_CTL)
- x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT)
- x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK)
- x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG)
- Watchdog Timer (WDT)
- Watchdog Timer Control
- x5040: Watchdog Timer Control Register (WDT_CTL)
- x5041: Watchdog Timer Status Register (WDT_ST)
- UART
- UART Pin
- Transfer Clock
- Transfer Data Settings
- Data Transfer Control
- Receive Errors
- UART Interrupts
- IrDA Interface
- x4100: UART Status Register (UART_ST)
- x4101: UART Transmit Data Register (UART_TXD)
- x4102: UART Receive Data Register (UART_RXD)
- x4103: UART Mode Register (UART_MOD)
- x4104: UART Control Register (UART_CTL)
- x4105: UART Expansion Register (UART_EXP)
- SPI Configuration
- SPI Input/Output Pins
- SPI Clock
- Data Transfer Condition Settings
- SPI Interrupts
- x4320: SPI Status Register (SPI_ST)
- x4322: SPI Transmit Data Register (SPI_TXD)
- x4324: SPI Receive Data Register (SPI_RXD)
- x4326: SPI Control Register (SPI_CTL)
- Settings Before Data Transfer
- I 2 C Interrupts
- Remote Controller (REMC)
- REMC Input/output Pin
- Carrier Generation
- Data Length Counter Clock Settings
- REMC Interrupts
- x5340: REMC Configuration Register (REMC_CFG)
- x5341: REMC Prescaler Clock Select Register (REMC_PSC)
- x5342: REMC H Carrier Length Setup Register (REMC_CARH)
- x5343: REMC L Carrier Length Setup Register (REMC_CARL)
- x5344: REMC Status Register (REMC_ST)
- x5345: REMC Length Counter Register (REMC_LCNT)
- x5346: REMC Interrupt Mask Register (REMC_IMSK)
- x5347: REMC Interrupt Flag Register (REMC_IFLG)
- On-chip Debugger (DBG)
- Debug Break Operation Status
- x5322: OSC1 Peripheral Control Register (MISC_OSC1)
- xffff90: Debug RAM Base Register (DBRAM)
- Basic External Connection Diagram
- Electrical Characteristics
- DC Characteristics
- Consumption Current
- AC Characteristics
- External Clock Input AC Characteristics
- Oscillation Characteristics
- Appendix A I/O Register List
- Appendix B Power Saving
- Appendix C Mounting Precautions
- Appendix D Initialization Routine
- Appendix E S1C17001 Mask ROM Code Development
- Appendix F Revision History