10 INPUT/OUTPUT PORT (P)88 EPSON S1C17001 TECHNICAL MANUAL10.6 P0 Port Chattering Filter FunctionThe P0 port includes a chattering filter circuit for key entry, which you can select to use or not use (and for whichyou can select a verification time if used) individually for the four P0[3:0] and P0[7:4] ports using P0CFx[2:0](P0_CHAT register).∗ P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)Register (D[2:0]/0x5208)∗ P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)Register (D[6:4]/0x5208)Table 10.6.1: Chattering filter function settingsP0CFx[2:0] Verification time *0x7 16384/f PCLK (8ms)0x6 8192/fPCLK (4ms)0x5 4096/fPCLK (2ms)0x4 2048/fPCLK (1ms)0x3 1024/fPCLK (512μs)0x2 512/fPCLK (256μs)0x1 256/fPCLK (128μs)0x0 No verification time(Off)(Default: 0x0, *when OSC3 = 2 MHz and PCLK = OSC3)Note: • The chattering filter verification time refers to the maximum pulse width that can be filtered.Generating an input interrupt requires a minimum input time of the verification time and amaximum input time of twice the verification time.• Input interrupts will not be accepted for a transition into SLEEP mode with the chatteringfilter left on. The chattering filter should be set off (no verification time) before executing theslp command.• P0 port interrupts must be blocked when P0_CHAT register (0x5208) settings are beingchanged. Changing the setting while interrupts are permitted may generate inadvertent P0interrupts.• A phenomenon may occur in which the internal signal oscillates due to the time elapseduntil the signal reaches the threshold value if the input signal rise-up/drop-off time is de-layed. Since input interrupts will malfunction under these conditions, the input signal rise-up/drop-off time should normally be set to 25 ns or less.
