Abov MC96F6432 Series manuals

MC96F6432 Series

Brand: Abov | Category: Microcontrollers

Table of contents

1. Table Of Contents
2. Table Of Contents
3. Table Of Contents
4. Table Of Contents
5. Table Of Contents
6. Table Of Contents
7. Table Of Contents
8. Table Of Contents
9. Overview
10. Features
11. Ordering Information
12. Development Tools
13. Figure 1.2 E-PGM+(Single writer)
14. Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
15. Block Diagram
16. Pin Assignment
17. Figure 3.2 MC96F6432Q 44MQFP-1010 Pin Assignment
18. Figure 3.3 MC96F6332L 32LQFP Pin Assignment
19. Figure 3.4 MC96F6332D 32SOP Pin Assignment
20. Package Diagram
21. Figure 4.2 44-Pin MQFP Package
22. Figure 4.3 32-Pin LQFP Package
23. Figure 4.4 32-Pin SOP Package
24. Figure 4.5 28-Pin SOP Package
25. Pin Description
26. Port Structures
27. External Interrupt I/O Port
28. Electrical Characteristics
29. A/D Converter Characteristics
30. Low Voltage Reset and Low Voltage Indicator Characteristics
31. High Internal RC Oscillator Characteristics
32. LCD Voltage Characteristics
33. DC Characteristics
34. AC Characteristics
35. SPI0/1/2 Characteristics
36. UART0/1 Characteristics
37. I2C0/1 Characteristics
38. Data Retention Voltage in Stop Mode
39. Internal Flash Rom Characteristics
40. Main Clock Oscillator Characteristics
41. Sub Clock Oscillator Characteristics
42. Main Oscillation Stabilization Characteristics
43. Operating Voltage Range
44. Recommended Circuit and Layout
45. Recommended Circuit and Layout with SMPS Power
46. Typical Characteristics
47. Figure 7.19 SUB RUN (IDD3) Current
48. Figure 7.21 STOP (IDD5) Current
49. Memory
50. Figure 8.1 Program Memory
51. Data Memory
52. Figure 8.3 Lower 128 Bytes RAM
53. XRAM Memory
54. Table 8-1 SFR Map Summary
55. Table 8-2 SFR Map Summary
56. Table 8-3 SFR Map
57. I/O Ports
58. Table 9-1 Port Register Map
59. Port Function
60. Interrupt Controller
61. External Interrupt
63. Interrupt Vector Table
64. Figure 10.3 Interrupt Sequence Flow
65. Effective Timing after Controlling Interrupt Bit
66. Multi Interrupt
67. Interrupt Enable Accept Timing
68. Interrupt Timing
69. Table 10-3 Interrupt Register Map
70. Peripheral Hardware
71. Table 11-1 Clock Generator Register Map
72. Basic Interval Timer
73. Table 11-2 Basic Interval Timer Register Map
74. Watch Dog Timer
75. Figure 11.4 Watch Dog Timer Block Diagram
76. Watch Timer
77. Table 11-4 Watch Timer Register Map
78. Timer 0
79. Figure 11.6 8-Bit Timer/Counter Mode for Timer 0
80. Figure 11.8 8-Bit PWM Mode for Timer 0
81. Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0
82. Figure 11.10 8-Bit Capture Mode for Timer 0
83. Figure 11.11 Input Capture Mode Operation for Timer 0
84. Figure 11.13 8-Bit Timer 0 Block Diagram
85. Table 11-6 Timer 0 Register Map
86. Timer 1
87. Figure 11.14 16-Bit Timer/Counter Mode for Timer 1
88. Figure 11.16 16-Bit Capture Mode for Timer 1
89. Figure 11.17 Input Capture Mode Operation for Timer 1
90. Figure 11.19 16-Bit PPG Mode for Timer 1
91. Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1
92. Figure 11.21 16-Bit Timer 1 Block Diagram
93. Timer 2
94. Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
95. Figure 11.23 16-Bit Timer/Counter 2 Example
96. Figure 11.24 16-Bit Capture Mode for Timer 2
97. Figure 11.25 Input Capture Mode Operation for Timer 2
98. Figure 11.27 16-Bit PPG Mode for Timer 2
99. Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2
100. Figure 11.29 16-Bit Timer 2 Block Diagram
101. Timer 3,
102. Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4
103. Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
104. Figure 11.32 8-Bit Capture Mode for Timer 3, 4
105. Figure 11.33 16-Bit Capture Mode for Timer 3
106. Table 11-12 PWM Frequency vs. Resolution at 8 MHz
107. Figure 11.34 10-Bit PWM Mode (Force 6-ch)
108. Figure 11.35 10-Bit PWM Mode (Force All-ch)
109. Figure 11.36 Example of PWM at 4 MHz
110. Figure 11.38 Example of PWM Output Waveform
111. Figure 11.40 Example of Phase Correction and Frequency correction of PWM
112. Figure 11.42 Example of Force Drive All Channel with A-ch
113. Figure 11.43 Example of Force Drive 6-ch Mode
114. Figure 11.44 Example of PWM Delay
115. Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
116. Figure 11.46 16-Bit Timer 3 Block Diagram
117. Table 11-14 Timer 3, 4 Register Map
118. Buzzer Driver
119. Table 11-16 Buzzer Driver Register Map
120. Figure 11.49 SPI 2 Block Diagram
121. Table 11-17 SPI 2 Register Map
122. Bit A/D Converter
123. Figure 11.52 12-bit ADC Block Diagram
124. Figure 11.55 ADC Operation for Align Bit
125. Figure 11.56 A/D Converter Operation Flow
126. USI0 (UART + SPI + I2C)
127. Figure 11.57 USI0 UART Block Diagram
128. Figure 11.58 Clock Generation Block Diagram (USI0)
129. Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
130. Figure 11.60 Frame Format (USI0)
131. Figure 11.61 Asynchronous Start Bit Sampling (USI0)
132. Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
133. Table 11-20 CPOL0 Functionality
134. Figure 11.64 USI0 SPI Clock Formats when CPHA0=0
135. Figure 11.65 USI0 SPI Clock Formats when CPHA0=1
136. Figure 11.66 USI0 SPI Block Diagram
137. Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
138. Figure 11.68 START and STOP Condition (USI0)
139. Figure 11.70 Acknowledge on the I2C-Bus (USI0)
140. Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0)
141. Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
142. Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
143. Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
144. Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
145. Figure 11.77 USI0 I2C Block Diagram
146. Table 11-21 USI0 Register Map
147. USI1 (UART + SPI + I2C)
148. Figure 11.78 USI1 UART Block Diagram
149. Figure 11.79 Clock Generation Block Diagram (USI1)
150. Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
151. Figure 11.81 Frame Format (USI1)
152. Figure 11.82 Asynchronous Start Bit Sampling (USI1)
153. Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
154. Table 11-23 CPOL1 Functionality
155. Figure 11.85 USI1 SPI Clock Formats when CPHA1=0
156. Figure 11.86 USI1 SPI Clock Formats when CPHA1=1
157. Figure 11.87 USI1 SPI Block Diagram
158. Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
159. Figure 11.89 START and STOP Condition (USI1)
160. Figure 11.91 Acknowledge on the I2C-Bus (USI1)
161. Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1)
162. Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
163. Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
164. Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
165. Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
166. Figure 11.98 USI1 I2C Block Diagram
167. Table 11-24 USI1 Register Map
168. Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
169. LCD Driver
170. Figure 11.99 LCD Circuit Block Diagram
171. Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
172. Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
173. Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
174. Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
175. Figure 11.104 Internal Resistor Bias Connection
176. Figure 11.105 External Resistor Bias Connection
177. Figure 11.106 LCD Circuit Block Diagram
178. Table 11-27 LCD Frame Frequency
179. Power Down Operation
180. IDLE Mode
181. STOP Mode
182. Release Operation of STOP Mode
183. Table 12-2 Power Down Operation Register Map
184. RESET
185. RESET Noise Canceller
186. Figure 13.5 Configuration Timing when Power-on
187. Table 13-2 Boot Process Description
188. External RESETB Input
189. Brown Out Detector Processor
190. LVI Block Diagram
191. Register Map
192. On-chip Debug System
193. Two-Pin External Interface
194. Figure 14.3 Data Transfer on the Twin Bus
195. Figure 14.5 Start and Stop Condition
196. Figure 14.7 Clock Synchronization during Wait Procedure
197. Figure 14.8 Connection of Transmission
198. Flash Memory
199. Figure 15.1 Flash Program ROM Structure
200. Table 15-1Flash Memory Register Map
201. Figure 15.2 Flow of Protection for Invalid Erase/Write
202. Configure Option
203. APPENDIX